Floating Point Multiplier Partial Product Alignment Circuit
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Solution Overview
Problem
Existing data processing systems face inefficiencies in handling subnormal floating point numbers, as they require additional hardware and delay to align and round results, which is not effectively addressed by current hardware mechanisms.
Innovation Solution
Incorporating shifting circuitry to align partial products before addition and rounding, allowing for integrated rounding within the adder circuitry, reducing delay and hardware overhead while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If subnormal numbers are handled in hardware, then processing speed is improved, but additional hardware overhead and delay are introduced for alignment and rounding
Solution Approach 1:
The patent combines the alignment shifting operation with the rounding operation by integrating the shifter into the adder circuitry. The shifter is incorporated directly into the adder structure, allowing both operations to be performed simultaneously in a single hardware unit rather than as separate sequential operations, thereby reducing hardware overhead and processing delay
Solution Approach 2:
The adder circuitry is designed to perform multiple functions: it acts as both an adder for combining partial products and as a shifter for aligning subnormal results. This multi-functional design eliminates the need for dedicated separate shifter hardware, reducing overall device complexity while maintaining the ability to handle subnormal numbers efficiently
2Device complexity
If subnormal numbers are treated as exceptions and handled in software, then hardware complexity is reduced, but processing performance deteriorates
Solution Approach 1:
The patent performs alignment shifting as a preliminary action within the hardware pipeline, specifically incorporating the shifter into the adder circuitry so that alignment is completed before the final rounding and output stages. This preliminary hardware-based alignment prevents the need for subsequent software intervention, maintaining both low hardware complexity and high processing performance
Data Source
AI summary
A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry 100 analyzes the exponents of the input operands A and B as well as counting the leading zeros in the fractional portions of these operands to determine an amount of left shift or right shift to be applied by shifting circuitry 200, 202 within the multiplier data path. This shift amount is applied so as to align the partial products so that when they are added they will produce the result C without requiring this to be further shifted. Furthermore, shifting the partial products to the correct alignment in this way in advance of adding these partial products permits injection rounding combined with the adding of the partial products to be employed for cases including subnormal values.