Floating Point Multiplier Rounding Logic Using Half Adders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing floating-point multiplication methods require serial processing and are slowed by the use of full adders for rounding, which increases cycle time and delays the rounding evaluation until the final product is produced.
Innovation Solution
A data processing apparatus using half adder logic to generate carry and sum bits for most significant bits of 2n-bit vectors, allowing for rounding increments to be injected efficiently without full adders, with separate adder logic for non-overflow and overflow conditions, and selector logic to derive the n-bit result from rounded results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full adders are used to inject rounding increments, then rounding can be performed, but cycle time increases and processing speed decreases
Solution Approach 1:
The patent segments the addition operation into two distinct paths: one for normal rounding (using half adders) and one for overflow rounding (using full adders). This segmentation allows the system to use the faster half adder path for the common case while preserving the ability to handle overflow cases correctly when needed.
Solution Approach 2:
The patent performs preliminary action by pre-calculating the most significant bits using half adders before the rounding decision is made. This allows the rounding increment to be injected at the appropriate position without requiring a full adder, as the carry propagation has already been handled by the half adder structure.
2Device complexity
If serial processing is used for floating point multiplication, then processing is simpler, but productivity decreases
Solution Approach 1:
The patent performs preliminary rounding evaluation and increment injection before the final summation of the 2n-bit vectors. This allows overlapping of operations where rounding can be prepared in advance while the multiplication is still being computed, effectively hiding the rounding delay and improving throughput.
Solution Approach 2:
The patent segments the floating point multiplication into independent parallel paths: exponent addition, significand multiplication, and rounding evaluation. These segments can be processed simultaneously rather than sequentially, improving productivity while maintaining manageable complexity through modular design.
3Measurement precision
If rounding evaluation waits for final product production, then rounding accuracy is ensured, but loss of time increases
Solution Approach 1:
The patent performs preliminary rounding evaluation using the most significant bits that are available before the complete final product is produced. The half adder logic pre-computes the carry and sum bits for the most significant positions, allowing rounding decisions to be made early without waiting for the entire multiplication to complete.
Solution Approach 2:
The patent rushes through the rounding evaluation by injecting the rounding increment at the predetermined position using half adder logic, skipping the wait time that would normally be required for complete product availability. This allows the rounding to proceed in parallel with the final summation operations.
Data Source
AI summary
A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation with a first rounded result and a second adder logic performs a second sum operation with a second rounded result. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.