Distributed Floating-Point Multiplier Blocks With Parallel Rounding
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Solution Overview
Problem
Existing specialized processing blocks in integrated circuits are limited to fixed-point operators, and implementing floating-point operators, particularly double-precision floating-point operators, is inefficient and requires additional logic outside the blocks.
Innovation Solution
Incorporating specialized processing blocks with inter-block signaling circuits and arithmetic operator circuits to perform double-precision floating-point multiplication by generating and combining partial products in parallel, allowing for simultaneous computation of normalization and rounding signals, thereby enhancing the blocks' adaptability to fixed-point, single-precision, and double-precision floating-point operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If floating-point operators are implemented using general-purpose programmable logic outside specialized processing blocks, then floating-point operations can be performed, but device complexity and resource overhead increase
Solution Approach 1:
The patent merges floating-point operation capabilities directly into specialized processing blocks by integrating arithmetic operator circuits that can perform both fixed-point and floating-point operations. This consolidation eliminates the need for separate general-purpose logic circuits, reducing overall device complexity while maintaining adaptability for different operation types.
Solution Approach 2:
The specialized processing blocks are designed with universal arithmetic operator circuits that can execute multiple operation types (fixed-point addition, fixed-point multiplication, single-precision floating-point, and double-precision floating-point) within the same hardware structure. This multi-functionality allows a single block to replace what would traditionally require multiple specialized circuits.
2Measurement precision
If double-precision floating-point multiplication is performed using traditional methods with separate logic circuits, then the operation can be completed, but computation latency increases
Solution Approach 1:
The double-precision floating-point multiplication is segmented into distinct operational phases: normalization of input operands, parallel computation of partial products, exponent calculation, and rounding. Each phase is handled by dedicated circuit components within the arithmetic operator, allowing simultaneous execution of independent sub-tasks and reducing overall computation latency while maintaining full double-precision accuracy.
Solution Approach 2:
The arithmetic operator circuits perform preliminary normalization of input operands and pre-computation of exponent differences before the main multiplication operation. By preparing data in advance and establishing the computational framework upfront, the circuit reduces the time required for the critical multiplication and rounding phases, thereby reducing overall latency without compromising precision.
3Device complexity
If specialized processing blocks are designed for fixed-point operations only, then device complexity is reduced, but adaptability to floating-point operations is limited
Solution Approach 1:
The specialized processing blocks incorporate dynamic configuration capabilities where the arithmetic operator circuits can be programmatically configured to perform different operation types based on input data characteristics. Control logic dynamically adjusts the operational mode (fixed-point addition, fixed-point multiplication, single-precision floating-point, or double-precision floating-point) without requiring physical reconfiguration, thus maintaining structural simplicity while achieving high adaptability.
Data Source
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AI summary
The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point multiplication operation. Inter-block signaling circuits may generate rounding information and propagate the rounding information together with partial product results from a current specialized processing block to another specialized processing block.