Floating Point Multiplier Rounding Adder for Subnormal Results
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Solution Overview
Problem
Existing data processing systems face performance issues when handling subnormal floating point results due to the need for additional hardware and delay in shifting and rounding, especially when dealing with the alignment of adder output for correct rounding.
Innovation Solution
A data processing apparatus that computes a result exponent for normalized operands, generates a rounding value by shifting a rounding constant based on the result exponent, and adjusts the significand accordingly to ensure correct rounding, incorporating guard and sticky bits for precise rounding, thereby eliminating the need for extra shift stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If subnormal results are handled in hardware with additional shifting and rounding adders, then correct rounding for subnormal results is achieved, but hardware complexity and processing delay increase
Solution Approach 1:
The rounding adder is designed to perform multiple functions: it handles both normal and subnormal result rounding operations, and can also perform the shifting function that was previously required separately. This multi-functional design eliminates the need for additional dedicated shifting hardware and rounding adders, reducing overall hardware complexity while maintaining correct rounding accuracy for subnormal results.
Solution Approach 2:
The patent combines the shifting operation and rounding addition operation into a single unified rounding adder unit. Instead of having separate shift stages and rounding adders, the rounding adder directly incorporates the shifting functionality, merging multiple operations into one hardware unit. This reduces the number of discrete components and interconnections, thereby reducing hardware complexity and processing delay.
2Manufacturing precision
If an extra multiplication cycle is used to shift partial products before adding and rounding, then correct rounding for subnormal results is achieved, but processing time increases
Solution Approach 1:
The rounding adder is pre-configured with the capability to perform shifting operations before the actual rounding addition. By having the shifting functionality built-in and ready in advance within the rounding adder unit, the system eliminates the need for separate preliminary shift stages that would consume additional multiplication cycles. The shifting and rounding can be performed in a more integrated and time-efficient manner within the same hardware unit.
Solution Approach 2:
By merging the shift operation and rounding addition into a single unified rounding adder unit, the patent enables these operations to be performed in a more efficient pipeline without requiring separate time cycles. The combined unit can process both operations in a streamlined sequence, reducing the total processing time compared to having separate dedicated units that would require sequential execution across multiple cycles.
3Manufacturing precision
If adder output is shifted and rounded using a further adder for subnormal results, then correct rounding is achieved, but processing delay increases
Solution Approach 1:
The patent merges the shifting function and the rounding addition function into a single rounding adder unit. This eliminates the need for a second sequential adder operation that would be required in traditional designs. By combining these functions, the system performs both operations in a single unified hardware unit, significantly reducing the processing delay that would result from sequential operations through multiple adder stages.
Solution Approach 2:
The rounding adder is designed as a universal unit that can perform both shifting and rounding addition operations. This multi-functional design allows the system to achieve correct rounding for subnormal results without requiring additional dedicated hardware units, thereby reducing the overall processing delay that would result from having multiple specialized units operating in sequence.
Data Source
AI summary
A data processing apparatus and method are provided for multiplying first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalized version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalized floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalized result significand. Thereafter, the normalized result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, while correctly rounding the result in situations where the result is subnormal.