Floating-Point Normalizer Circuit with Mantissa Alignment
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Solution Overview
Problem
Existing floating-point arithmetic systems face challenges in normalizing and denormalizing data efficiently, particularly in handling results with exponents smaller than 0, which require format conversion and shifting operations.
Innovation Solution
A normalizer circuit comprising a mantissa alignment circuit, a '1' search circuit, an exponent addition circuit, and a normalization circuit that shifts mantissa data, searches for a leading '1', and adjusts exponent data to perform normalization or denormalization based on specific conditions, ensuring efficient format conversion and data representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If normalization is performed by searching for a leading '1' and performing shifting on the mantissa, then normalization accuracy is improved, but device complexity increases due to additional search and shift circuits
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the mantissa alignment before the normalization process. The mantissa alignment circuit performs an initial left shift by one bit, positioning the binary point optimally before the leading '1' search begins. This preliminary positioning reduces the search range and simplifies the subsequent normalization process, thereby improving efficiency without significantly increasing circuit complexity.
Solution Approach 2:
The normalization process is segmented into distinct functional modules: mantissa alignment circuit, leading '1' search circuit, exponent addition circuit, and normalization control circuit. Each module performs a specific sub-function, making the overall complex process manageable and implementable with standardized circuit blocks. This segmentation allows for optimized design of each component while maintaining overall system accuracy.
2Adaptability or versatility
If denormalization is performed to convert result data into denormalized format with exponent fixed to '0' and hidden bit set to '0', then data format compatibility is improved, but processing time increases due to additional format conversion steps
Solution Approach 1:
The patent performs preliminary exponent adjustment by adding the shift amount to the original exponent before finalizing the denormalized format. This preliminary calculation prepares the exponent value in advance, so that when denormalization is required, the conversion can be executed quickly by simply fixing the exponent to '0' and hidden bit to '0', rather than performing complex calculations during the format conversion itself.
Solution Approach 2:
The patent introduces an intermediate normalized format as a mediator between the raw computation result and the final denormalized output. The normalization process creates a standardized intermediate representation that simplifies subsequent denormalization operations. This intermediate form acts as a buffer that makes the final format conversion more efficient and predictable.
3Productivity
If the binary point is shifted left by one bit in the mantissa alignment circuit, then normalization efficiency is improved, but the risk of losing precision increases due to potential bit overflow
Solution Approach 1:
The patent applies beforehand cushioning by designing the mantissa alignment circuit with sufficient bit width to accommodate the left shift operation. The circuit is prepared in advance with extra guard bits and proper overflow detection mechanisms, ensuring that when the binary point shifts left by one bit, no precision is lost. This cushioning capacity is built into the circuit architecture to prevent precision loss under normal operating conditions.
Data Source
AI summary
A normalizer receives input data including first exponent data and first mantissa data and generates normalized output data. The normalizer includes a mantissa alignment circuit, a “1” search circuit, an exponent addition circuit, a normalization circuit. The mantissa alignment circuit outputs second mantissa data including a binary point shifted by one bit to the left in comparison to a binary point of the first mantissa data. The “1” search circuit searches for an uppermost bit position of a leading “1” in the second mantissa data to output shift data. The exponent addition circuit performs an addition operation on the shift data and the first exponent data and configured to perform a “+1” operation on a result of the addition operation to output addition data. The normalization circuit performs normalization when the addition data corresponds to a normalization condition, the normalization being performed by outputting the addition data as exponent data of the output data and outputting result data that is obtained by shifting the second mantissa data by the number of bits that correspond to an absolute value of the shift data as mantissa data of the output data.