Floating-Point to Integer Conversion Using Parallel Shift Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing number format conversion circuits in digital circuits face performance limitations such as gate delay, logic depth, power consumption, and circuit throughput when converting between floating point and signed integer representations.
Innovation Solution
A method and apparatus that includes a shift conditioning module, a two's complement module, and a shift execution module to convert a floating point representation to a signed integer representation, utilizing parallel operations to improve performance by generating a shift control signal based on the exponent and shifting the pre-shift output by a specified number of bit positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prior art conversion circuits are used to convert floating point to signed integer representation, then the conversion function is provided, but gate delay and logic depth increase reducing performance
Solution Approach 1:
The conversion circuit is divided into three independent modules: a shift conditioning module that generates control signals from the exponent, a two's complement module that processes the mantissa in parallel, and a shift execution module that performs the final shifting. This segmentation allows each module to operate independently and in parallel, reducing the overall logic depth and gate delay compared to sequential prior art approaches.
Solution Approach 2:
The shift conditioning module performs preliminary processing of the exponent to generate the shift control signal before the shift execution module needs it. The two's complement module simultaneously prepares the mantissa in parallel. This preliminary action ensures that all inputs to the shift execution module are ready simultaneously, minimizing waiting time and reducing overall conversion delay.
2Use of energy by moving object
If prior art conversion circuits are used, then floating point to integer conversion is achieved, but power consumption is high
Solution Approach 1:
By segmenting the conversion circuit into three specialized modules, each module can be optimized for its specific function with minimal transistors. The shift conditioning module only processes the exponent, the two's complement module only processes the mantissa, and the shift execution module only performs shifting. This functional segmentation reduces the total transistor count and power consumption while maintaining high conversion throughput through parallel operation.
Solution Approach 2:
The invention merges the shift control signal generation and the two's complement operation into simultaneously executing parallel processes that feed into a single shift execution module. This merging of parallel operations reduces the overall circuit area and power consumption compared to sequential implementations, while the unified shift execution module maximizes throughput by processing both conditions in one operation.
3Productivity
If prior art conversion circuits are used, then format conversion is provided, but circuit throughput is limited
Solution Approach 1:
The conversion circuit is segmented into three parallel-operating modules: shift conditioning, two's complement, and shift execution. Each module processes its portion of the conversion simultaneously without waiting for the others, eliminating sequential bottlenecks. This parallel segmentation dramatically increases circuit throughput and reduces the total conversion time compared to prior art sequential approaches.
Solution Approach 2:
The shift conditioning module generates the shift control signal in advance during the same time period that the two's complement module processes the mantissa. This preliminary generation of control signals eliminates waiting time in the shift execution stage, maximizing throughput. The conversion time is reduced because no stage needs to wait for the completion of a previous stage.
Data Source
AI summary
Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.