Floating-Point Power Function Corner Check Circuitry
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Solution Overview
Problem
The floating-point power function in graphics and compute applications requires numerous instructions to check corner cases, leading to increased processing time and power consumption.
Innovation Solution
Incorporating corner check circuitry that executes a single instruction to check all corner cases for the power function, potentially sharing circuitry with other datapaths, such as odd integer detection circuitry, to reduce code size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software libraries use multiple instructions to implement the power function and check corner cases, then corner case detection is thorough, but processing time and power consumption increase substantially
Solution Approach 1:
The patent replaces the mechanical system of sequential software instructions with an electronic circuit system that performs corner case detection in parallel. The corner check circuitry simultaneously evaluates multiple corner conditions (such as x=0, y=0, x=1, y=1, and other boundary conditions) using hardware logic gates and comparators, eliminating the need for sequential instruction execution while maintaining thorough detection of all corner cases.
Solution Approach 2:
The patent segments the power function computation into two independent parallel paths: a corner case detection path and a main computation path. The corner check circuitry separately evaluates corner conditions while the main computation unit simultaneously calculates the power function for normal cases. This segmentation allows both operations to proceed concurrently without interfering with each other, reducing overall processing time.
2Reliability
If software libraries use multiple instructions to implement the power function and check corner cases, then corner case detection is thorough, but power consumption increases substantially
Solution Approach 1:
The patent replaces the energy-consuming sequential software instruction execution with a hardware circuit system that performs corner case detection simultaneously with the main computation. The corner check circuitry uses logic gates and comparators that consume minimal power compared to the cumulative power consumption of multiple sequential instructions, while achieving the same reliability in corner case detection.
Solution Approach 2:
The patent merges the corner case detection function with the main power function computation into a unified circuit architecture. Both the corner check circuitry and the main computation unit operate in parallel within the same hardware structure, sharing common resources such as input buffers and output routing. This merging eliminates the need for separate execution phases, reducing overall power consumption while maintaining thorough corner case detection.
3Productivity
If a single instruction is used to check all corner cases, then code size is reduced and performance increases, but circuit complexity increases
Solution Approach 1:
The patent implements a universal corner check circuitry that handles multiple corner cases (x=0, y=0, x=1, y=1, negative zero, infinity, NaN, and other boundary conditions) through a unified hardware structure. The circuit uses configurable comparators and logic gates that can be programmed or configured to detect different corner conditions, eliminating the need for separate dedicated circuits for each corner case while maintaining comprehensive detection capability.
Solution Approach 2:
The patent transitions from the software dimension (multiple sequential instructions) to the hardware dimension (parallel circuit operations). By implementing corner case detection in the hardware domain using logic circuits and comparators, the system achieves simultaneous evaluation of multiple corner conditions without the sequential overhead of software instructions. This dimensional change enables single-instruction execution while maintaining thorough corner case detection.
Data Source
AI summary
Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2(second input*log<sub2>2</sub2>(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.