Floating Point Power Function Hardware Verification
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Solution Overview
Problem
Hardware designs implementing floating point power functions are challenging to verify due to their complexity, especially when using simulation-based verification methods, which are time-consuming and prone to errors, while formal verification struggles with the complexity of floating point power functions with allowable errors.
Innovation Solution
The method involves formally verifying that the hardware design is recurrent over sets of β input exponents, followed by exhaustive simulation over a reduced simulation range to verify the property, leveraging the recurrent nature of hardware designs to efficiently validate floating point power functions using a combination of formal and simulation-based verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation-based verification is used to verify hardware designs for floating point power functions, then verification can be performed, but the verification time becomes excessively long (days or weeks) and the process becomes unmanageable
Solution Approach 1:
The verification process is segmented into two distinct phases: formal verification to prove recurrency properties for all possible inputs, and simulation-based verification only for a reduced set of β input exponents. This segmentation allows the majority of verification to be done efficiently through formal methods while using simulation only where necessary, dramatically reducing total verification time from days/weeks to minutes/hours.
Solution Approach 2:
The patent extracts and proves the recurrency property formally, removing the need to simulate all possible input combinations. By taking out the recurrency verification from the simulation process and handling it separately through formal verification, the simulation scope is reduced to only β input exponents, eliminating the time-consuming exhaustive simulation of all possible inputs.
2Reliability
If formal verification is used to verify hardware designs for floating point power functions, then verification completeness improves, but the complexity of verification increases due to allowable errors in floating point operations
Solution Approach 1:
The patent extracts the recurrency property from the complex floating point power function verification and proves it separately using formal verification. This extraction simplifies the overall verification by separating the recurrency aspect (which can be proven formally) from the error bound verification (which uses simulation on a reduced set), making the verification process manageable despite floating point complexities.
Solution Approach 2:
The patent changes the verification approach by introducing the recurrency parameter β (where β is a multiple of the reciprocal of the power function exponent). This parameter allows the verification to be performed on a reduced set of inputs while maintaining completeness, effectively transforming an intractable verification problem into a manageable one by changing how the verification space is parameterized.
3Measurement precision
If exhaustive simulation is performed to verify all possible inputs, then verification accuracy is ensured, but the number of simulation vectors becomes unmanageable and the process takes days or weeks
Solution Approach 1:
The verification is segmented into formal verification of recurrency (which covers all inputs theoretically) and simulation of a reduced set of β input exponents. This segmentation reduces the number of simulation vectors from all possible inputs to only β representatives, maintaining verification accuracy through the formal recurrency proof while dramatically reducing the simulation workload.
Solution Approach 2:
Instead of simulating all possible inputs directly, the patent uses formal verification to create a proof model that copies the behavior across all inputs satisfying the recurrency property. This allows verification accuracy for all inputs to be achieved by simulating and formally proving properties for only a subset of β input exponents.
Data Source
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AI summary
A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only β input exponents.