Two-Phase Verification for Floating Point Product Hardware
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Solution Overview
Problem
Formal verification of hardware designs for integrated circuits implementing floating point products of power functions is challenging due to the large input space and complex floating point operations, making it difficult to exhaustively verify properties using existing methods.
Innovation Solution
A two-phase verification approach is introduced, where the first phase formally verifies outputs for pairs of non-exception input sets with specific relationships, reducing the number of verifications needed in the second phase, and focusing on subsets of input sets with integer exponent differences to efficiently verify properties using formal verification tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is applied to hardware designs for floating point product of power functions, then verification thoroughness is improved, but verification complexity and time consumption increase significantly
Solution Approach 1:
The verification process is divided into two distinct phases: a first phase that formally verifies properties for a subset of input sets with integer exponent differences, and a second phase that verifies properties for remaining input sets using simulation-based methods. This segmentation reduces the complexity of the overall verification task by handling different input spaces with appropriate methods, making the verification process more manageable and less time-consuming while maintaining thoroughness.
Solution Approach 2:
The invention changes the verification parameters by focusing on integer exponent differences in the first phase, which simplifies the mathematical properties that need to be verified. By transforming the verification problem into one involving integer arithmetic rather than general floating point arithmetic, the formal verification becomes more tractable and less complex, while still providing meaningful verification coverage.
2Reliability
If exhaustive verification of all input sets is performed, then verification completeness is improved, but verification time increases significantly
Solution Approach 1:
The verification process is divided into two phases where the first phase handles a subset of input sets with integer exponent differences using formal verification, and the second phase handles remaining input sets using simulation-based verification. This segmentation allows the system to verify completeness efficiently by applying the most appropriate verification method to different portions of the input space, significantly reducing total verification time while maintaining completeness.
Solution Approach 2:
The invention applies partial formal verification to a specific subset of input sets (those with integer exponent differences) rather than attempting to verify all input sets exhaustively. This partial action approach provides sufficient verification coverage for the most critical cases while avoiding the time-consuming exhaustive verification of all possible inputs, thus achieving verification completeness in practice without excessive time consumption.
3Measurement precision
If formal verification is applied to all input sets, then verification accuracy is improved, but computational resources required increase
Solution Approach 1:
The verification process segments input sets into two categories: those with integer exponent differences handled by formal verification for high accuracy, and those without handled by simulation-based verification. This segmentation applies computational resources efficiently by using the more resource-intensive formal verification only where it provides the most benefit, reducing overall computational resource consumption while maintaining verification accuracy for critical cases.
Solution Approach 2:
The invention changes the verification approach based on parameter characteristics, specifically whether exponent differences are integers. This parameter-based differentiation allows the system to use formal verification (higher accuracy) only when the integer exponent difference property holds, which occurs for a subset of inputs, thereby reducing unnecessary computational resource expenditure on cases where simulation-based verification suffices.
Data Source
AI summary
Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t<sub2>0</sub2>× . . . ×xnt<sub2>n</sub2>, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X′ and Y′ with a same mantissa and X′exp−(t0X0.exp+ . . . +tnXn.exp)=Y′exp−(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer.