Floating-Point Quantum Circuit Libraries for Fault-Tolerant Arithmetic
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Solution Overview
Problem
Quantum computing algorithms for practical problems in quantum chemistry and materials science require significant arithmetic operations, which are inefficiently handled in existing fault-tolerant gate sets, leading to high qubit and gate counts for floating-point arithmetic operations.
Innovation Solution
A quantum circuit library is developed for floating-point addition and multiplication, using synthesis tools to generate optimized circuits from classical Verilog implementations, combining human-generated and automated optimization methods with fault-tolerant and universal gate sets, reducing qubit and gate counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault-tolerant gate sets are used for floating-point arithmetic operations, then reliability is improved, but device complexity and qubit usage increase significantly
Solution Approach 1:
The floating-point arithmetic operations are decomposed into modular quantum circuit components including separate modules for exponent comparison, mantissa alignment, addition, and normalization. Each module is independently optimized using fault-tolerant gate sets, allowing selective application of error correction only where critical while reducing overall circuit complexity.
Solution Approach 2:
The patent transforms floating-point arithmetic parameters by converting between different representations (e.g., sign-magnitude to two's complement) and adjusting precision parameters dynamically. This allows the circuit to operate with reduced qubit requirements while maintaining fault tolerance through parameter optimization rather than brute-force redundancy.
2Productivity
If automated synthesis tools are used to generate quantum circuits from classical Verilog, then productivity is improved, but manufacturing precision may be compromised
Solution Approach 1:
The synthesis process incorporates preliminary manual optimization of critical circuit paths before automated generation. Key modules such as the exponent comparison logic and normalization circuits are pre-optimized by experts, then integrated with automatically generated components to maintain both efficiency and precision.
Solution Approach 2:
The patent implements iterative verification and optimization loops where synthesized circuits are simulated, tested for correctness, and refined through multiple passes. Automated tools generate initial circuits which are then validated against mathematical correctness criteria and optimized further based on performance feedback, ensuring both productivity and precision.
Data Source
AI summary
Quantum algorithms to solve practical problems in quantum chemistry, materials science, and matrix inversion often involve a significant amount of arithmetic operations. These arithmetic operations are to be carried out in a way that is amenable to the underlying fault-tolerant gate set, leading to an optimization problem to come close to the Pareto-optimal front between number of qubits and overall circuit size. In this disclosure, a quantum circuit library is provided for floating-point addition and multiplication. Circuits are presented that are automatically generated from classical Verilog implementations using synthesis tools and compared with hand-generated and hand-optimized circuits. Example circuits were constructed and tested using the software tools LIQUi| and RevKit.