Image Sensor ADC With Floating-Point Ramp for Faster HDR Readout
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Solution Overview
Problem
Conventional single slope analog-to-digital converters (ADCs) in image sensors are slow and power-consuming, especially in high dynamic range (HDR) imaging systems, due to their reliance on a long ramp that covers the entire full scale range.
Innovation Solution
The method involves attenuating the input signal until it falls below a predetermined threshold, using a short ramp to determine the voltage level, and computing the ADC output based on the attenuation factor and ramp determination, represented as exponent and mantissa values in a floating-point format, allowing for faster and more power-efficient conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single slope ramp ADCs are used to cover the entire full scale range, then measurement precision is maintained, but conversion time increases and power consumption increases
Solution Approach 1:
The patent divides the ADC conversion process into two segments: a first conversion stage that processes signals within a first dynamic range using a first ADC, and a second conversion stage that processes signals within a second dynamic range using a second ADC. This segmentation allows each ADC to operate over a reduced range, decreasing the ramp time required for conversion while maintaining overall precision through coordinated operation of both converters
Solution Approach 2:
The patent implements dynamic range switching by selectively activating either the first ADC or the second ADC based on the input signal level. The system dynamically adjusts which converter is active and modifies the dynamic range of the active ADC, allowing optimal conversion speed for each signal condition without sacrificing measurement precision
2Measurement precision
If conventional single slope ramp ADCs are used to cover the entire full scale range, then measurement precision is maintained, but power consumption increases
Solution Approach 1:
The patent divides the ADC conversion process into two segments: a first conversion stage that processes signals within a first dynamic range using a first ADC, and a second conversion stage that processes signals within a second dynamic range using a second ADC. This segmentation allows each ADC to operate over a reduced range, decreasing the ramp time required for conversion while maintaining overall precision through coordinated operation of both converters
Solution Approach 2:
The patent uses a dual-ADC architecture where only one ADC is actively converting at any given time, while the other can be in a lower-power state. By partially utilizing the full conversion capability in each stage (each ADC handles only a portion of the total dynamic range), the system reduces overall power consumption while maintaining full precision through the combined operation of both converters
3Adaptability or versatility
If the number of signal conversions is increased for HDR imaging, then imaging dynamic range is improved, but conversion time increases and power consumption increases
Solution Approach 1:
The patent divides the ADC conversion process into two segments: a first conversion stage that processes signals within a first dynamic range using a first ADC, and a second conversion stage that processes signals within a second dynamic range using a second ADC. This segmentation allows each ADC to operate over a reduced range, decreasing the ramp time required for conversion while maintaining overall precision through coordinated operation of both converters
Solution Approach 2:
The patent implements dynamic range switching by selectively activating either the first ADC or the second ADC based on the input signal level. The system dynamically adjusts which converter is active and modifies the dynamic range of the active ADC, allowing optimal conversion speed for each signal condition without sacrificing measurement precision
Data Source
AI summary
An image sensor may include an array of image sensor pixels that are read out using analog-to-digital converters (ADCs). The ADC may be shot-noise-matched to reduce the number of decision cycles required. A ramp with limited resolution spanning only a small portion of the full scale voltage range may be used. For small analog input voltages, this limited ramp range is sufficient. For large analog input voltages, less resolution is needed due to the increasing shot noise in the photo signal. The larger input voltages may be successively divided by a selected attenuation factor until the analog input signal is within the range of the reduced ramp. The ADC keeps track of the number of divisions being performed to determine an exponent value for a floating-point output value and then convert the residual signal with the smaller ramp to determine a mantissa value for the floating-point output value.


