Floating-Point Pseudo Random Generator Using Segmented Bit Fields
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Solution Overview
Problem
Existing pseudo random number generators struggle to efficiently produce random numbers with floating-point representation, which are required for advanced applications like artificial intelligence and parallel computing systems.
Innovation Solution
A pseudo random number generator comprising a first generator to generate a bit sequence with floating-point representation and a second generator to modify the sign and exponent parts of this sequence, using a mask circuit and an adder circuit to produce pseudo random numbers within a specified interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a linear feedback shift register (LFSR) is used to generate pseudo random numbers, then the generation process is simple and efficient, but the output is limited to fixed-point representation and cannot directly provide floating-point representation required for AI applications
Solution Approach 1:
The patent divides the bit sequence into distinct segments corresponding to floating-point components: sign bit, exponent part, and mantissa part. The first generator handles the sign and exponent segments while the second generator processes the mantissa segment, allowing conversion from fixed-point to floating-point representation without complicating the overall generation process
Solution Approach 2:
The patent introduces an intermediary conversion mechanism that transforms the fixed-point bit sequence generated by the LFSR into floating-point representation. This intermediary process uses the segmented approach to reassemble the bits into proper floating-point format, bridging the gap between simple LFSR generation and AI application requirements
2Productivity
If conventional random number generation methods are used, then the hardware implementation is simple, but the generator cannot efficiently produce floating-point random numbers for parallel computing systems
Solution Approach 1:
The hardware is segmented into two independent generators: a first generator that produces the sign and exponent portions, and a second generator that produces the mantissa portion. This segmentation allows each generator to be optimized for its specific function while working together to produce complete floating-point numbers efficiently
Solution Approach 2:
The patent transitions from generating random numbers in one dimension (fixed-point) to multiple dimensions (floating-point with separate sign, exponent, and mantissa components). This dimensional expansion enables direct output in the floating-point format required by parallel computing systems without additional conversion steps
3Extent of automation
If a reconfigurable architecture with multiple processing elements is used, then parallel computation capability is enhanced, but the system requires efficient supply of floating-point random numbers to each row or column
Solution Approach 1:
The patent creates a universal random number generation architecture where the two generators can independently supply floating-point random numbers to any row or column of the reconfigurable matrix. The segmented design allows flexible distribution of random numbers across different processing elements, supporting various parallel computing configurations
Solution Approach 2:
The patent ensures continuous generation of floating-point random numbers through the parallel operation of two generators. The first generator continuously produces sign and exponent bits while the second generator continuously produces mantissa bits, maintaining uninterrupted supply of complete floating-point numbers to the parallel processing system
Data Source
AI summary
A pseudo random number generator includes a first generator configured to generate a random first bit sequence having a bit length with floating-point representation, and a second generator configured to generate a second bit sequence having the bit length, using a predetermined sign bit, a bit sequence of a predetermined exponent part, and a bit sequence of a mantissa part included in the first bit sequence.