Floating-Point Record Form Instruction Segmentation for Low Latency
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Solution Overview
Problem
Floating-point record form instructions in modern processors are slow due to the need to record exception bits from previous instructions, leading to late availability of result registers and conflicting requirements for out-of-order and in-order execution, which hinders the execution of subsequent dependent instructions.
Innovation Solution
Breaking down record form floating-point instructions into two internal instructions, where one executes out-of-order to compute the target register and the other executes in-order to compute the condition register, allowing for improved processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If record form FP instructions are executed in-order to ensure correct Condition Register (CR), then execution accuracy is maintained, but processing speed deteriorates due to late availability of result registers
Solution Approach 1:
The record form FP instruction is segmented into two separate internal instructions: a first internal instruction that executes out-of-order to compute the target floating-point register result, and a second internal instruction that executes in-order to compute the Condition Register. This segmentation allows the result computation to proceed without waiting for exception bit collection, while the CR update maintains proper ordering, thereby resolving the contradiction between speed and accuracy.
2Reliability
If record form FP instructions wait for all older instructions to complete before execution, then Condition Register correctness is ensured, but execution latency increases
Solution Approach 1:
By dividing the record form instruction into two internal instructions with different execution ordering requirements, the patent enables the result computation to start immediately without waiting for older instructions to complete. The CR computation internally waits for proper ordering, thus reducing overall execution latency while maintaining correctness.
Solution Approach 2:
The first internal instruction performs preliminary computation of the target floating-point register result out-of-order before the CR computation is complete. This preliminary action allows subsequent dependent instructions to execute earlier, reducing the overall execution latency while the second internal instruction ensures CR correctness by waiting for proper ordering.
3Productivity
If out-of-order execution is used to obtain result FRT early, then processing speed improves, but Condition Register correctness deteriorates due to premature execution
Solution Approach 1:
The patent segments the single record form instruction into two distinct internal instructions with different execution semantics. The first internal instruction is permitted to execute out-of-order for speed, while the second internal instruction maintains in-order execution for CR correctness. This segmentation allows each part to optimize for its specific requirement without compromising the other.
Data Source
AI summary
A computer processing system is provided. The computer processing system includes a processor configured to execute a record form instruction cracked into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form instruction.