Floating Point Rounding Processors Direct Significand Rounding

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Solution Overview

Problem

Current processors lack efficient instructions for rounding floating-point numbers to a specified number of fraction bits, requiring complex multi-step processes that involve scaling and descaling, which can increase computational overhead and resource usage.

Innovation Solution

The development of floating-point rounding instructions and processors capable of executing these instructions, which allow for direct rounding of significands to a specified number of fraction bits within a single operation, reducing the need for additional processing steps and improving precision control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If floating-point numbers are rounded using conventional multi-step processes involving scaling and descaling, then rounding functionality is achieved, but computational overhead and resource usage increase

Engineering Contradiction:
Improverounding processing efficiencyVSAvoidprocessing steps complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple conventional rounding steps (scaling, rounding, descaling) into a single integrated operation that directly rounds floating-point significands to a specified number of fraction bits. This consolidation eliminates intermediate scaling operations and reduces the number of processing steps while maintaining rounding accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The rounding operation is segmented to work directly on the significand field of the floating-point representation, allowing independent manipulation of the significant digits without affecting the exponent field. This segmentation enables direct rounding control at the fraction bit level without requiring global scaling operations.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If floating-point numbers are rounded using conventional multi-step processes, then rounding functionality is achieved, but computational overhead increases

Engineering Contradiction:
Improveprecision controlVSAvoidcomputational overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary identification of the target fraction bit position and configures the rounding operation parameters before executing the rounding. This preliminary setup allows the rounding to be performed in a single pass without requiring subsequent correction or adjustment steps, reducing overall computational overhead.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If direct rounding of significands is implemented, then processing efficiency is improved, but instruction set complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidinstruction set complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The rounding instruction is designed to be universal, handling various floating-point formats (single precision, double precision) and different rounding modes (round toward zero, round away from zero, round to nearest) through a single integrated operation. This multi-functionality reduces the need for multiple specialized instructions while maintaining processing efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10209986B2Floating point rounding processors, methods, systems, and instructions
Publication Date: 2019.02.19 INTEL CORP
  • US10209986B2 patent drawing
  • US10209986B2 patent drawing
  • US10209986B2 patent drawing

AI summary

A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.