Floating-Point Rounding via Relaxed Precision Constraints

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Solution Overview

Problem

Current methods for floating-point rounding in computer systems are inefficient, requiring excessive hardware resources and computation time due to the need for extra precision bits and complex rounding algorithms, which do not adequately address the challenge of representing results with finite precision.

Innovation Solution

A method that relaxes precision constraints for floating-point calculations, allowing only one quotient to be calculated and using comparison logic to select from three possible results (the original result, or results adjusted by one unit in the last place) to achieve accurate rounding with reduced hardware requirements and computation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If extra precision bits and complex rounding algorithms are used, then rounding accuracy is improved, but hardware resources and computation time increase

Engineering Contradiction:
Improverounding accuracyVSAvoidhardware resources
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter of precision requirements by relaxing the constraint from requiring extra precision bits to accepting lower precision intermediate results. The rounding unit determines the final accurate result through comparison logic rather than through high-precision calculation, thus reducing hardware complexity while maintaining rounding accuracy.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the rounding determination function from the calculation process. Instead of requiring the calculation unit to produce high-precision results, the rounding unit separately determines the correct rounded value by comparing the lower precision result with the rounding threshold, thus separating accuracy requirements from hardware complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If extra precision bits and complex rounding algorithms are used, then rounding accuracy is improved, but computation time increases

Engineering Contradiction:
Improverounding accuracyVSAvoidcomputation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the time parameter by reducing the computational complexity through lower precision intermediate calculations. The rounding unit compensates for the reduced precision by using comparison logic to determine the correct rounded result, thus reducing computation time while maintaining accuracy.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the rounding process into two independent stages: (1) calculation stage with relaxed precision requirements that produces a lower precision result, and (2) rounding determination stage that uses comparison logic to identify the correct rounded value. This segmentation allows each stage to be optimized independently, reducing overall computation time.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If relaxed precision constraints are used, then hardware resources are reduced, but rounding accuracy may be compromised

Engineering Contradiction:
Improvehardware resourcesVSAvoidrounding accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The rounding unit acts as an intermediary that bridges the gap between lower precision calculation results and the required rounding accuracy. It receives the lower precision result from the calculation unit and uses comparison logic with the rounding threshold to determine the correct rounded value, thus ensuring accuracy without requiring high-precision hardware throughout the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the precision parameter dynamically across different stages of the computation. The calculation unit operates with relaxed precision constraints to reduce hardware resources, while the rounding unit restores accuracy by determining the correct rounded result through comparison logic, thus achieving both resource efficiency and accuracy.

Inventive Principle:
Principle #35Parameter changes

4Loss of time

If one quotient is calculated instead of two, then computation time is reduced, but rounding accuracy may be compromised

Engineering Contradiction:
Improvecomputation timeVSAvoidrounding accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent extracts the rounding determination function from the calculation process. Instead of calculating two quotients to ensure accuracy, the system calculates one quotient with relaxed precision and extracts the correct rounded value through comparison logic in the rounding unit, thus reducing computation time while maintaining accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The rounding unit serves as an intermediary that compensates for the reduced precision from calculating only one quotient. It uses the lower precision result and applies comparison logic with the rounding threshold to determine the correct rounded result, thus maintaining accuracy without requiring multiple quotient calculations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8005884B2Relaxed remainder constraints with comparison rounding
Publication Date: 2011.08.23 ADVANCED MICRO DEVICES INC
  • US8005884B2 patent drawing
  • US8005884B2 patent drawing
  • US8005884B2 patent drawing

AI summary

A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may not be used. Only one quotient may be calculated, rather than two, further reducing needed hardware to perform the rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency is much smaller than a second floating-point multiply accumulate latency.