Floating Point Arithmetic Hardware Using Segmented Mantissa Representation
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Solution Overview
Problem
Existing floating point arithmetic technologies face challenges in efficiently supporting high-precision operations due to the significant increase in hardware size required, leading to a burden on hardware development and inefficiencies in chip area usage.
Innovation Solution
A method for representing high-precision floating point arithmetic as two low-precision floating point representations, allowing for hardware acceleration by storing and recombining bit information of the mantissa, and performing shift operations to align exponents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision floating point arithmetic is supported using traditional hardware, then calculation accuracy is improved, but hardware size increases proportionally to the square of precision
Solution Approach 1:
The patent divides a 64-bit double-precision floating point number into two 32-bit single-precision floating point numbers. This segmentation allows the system to represent high-precision values using multiple lower-precision components, reducing the hardware size required while maintaining calculation accuracy. The high-precision value is reconstructed by combining results from multiple low-precision operations.
2Adaptability or versatility
If hardware for high-precision arithmetic is added to support various precisions, then precision versatility is improved, but chip area is wasted when high-precision arithmetic is rarely needed
Solution Approach 1:
The patent enables a single low-precision hardware unit to perform multiple precision operations by representing high-precision values as combinations of low-precision values. This multi-functionality allows the same hardware to handle both low-precision and high-precision arithmetic without requiring separate dedicated hardware for each precision level, thus avoiding chip area waste while maintaining precision versatility.
3Measurement precision
If double-precision floating point representation is implemented, then numerical accuracy is improved, but hardware complexity increases four times compared to single-precision
Solution Approach 1:
The patent segments the complex 64-bit floating point operations into simpler 32-bit operations. By representing a double-precision value as two single-precision values and performing arithmetic operations on these segments separately, the system reduces the complexity of individual floating point units while maintaining the ability to perform high-precision calculations through combination of results.
Data Source
AI summary
An example of a floating point arithmetic method comprises: storing bit information of a mantissa of at least one operand selected from among at least two operands based on a result of comparing exponents of the at least two operands being input; outputting an operation result of higher bits by calculating the at least two operands; and outputting an operation result of lower bits by adding, to the bit information of the mantissa of the at least one operand, a bit lost through a normalization operation and a rounding operation in the calculation of the at least two operands. Accordingly, the method can accelerate high-precision arithmetic by adding, to a floating point operator, hardware that calculates an error in a floating point addition operation, and, via instructions supporting the same, can configure an efficient processor.