Floating-Point Significand Subtraction Latency Reduction
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Solution Overview
Problem
Subtracting significand values of floating-point operands that are close to each other results in significant latency due to the need for re-normalization, which is inefficient in current data processing systems.
Innovation Solution
An apparatus and method that utilize significand shift control circuitry to assert a shift signal based on exponent differences, allowing for parallel processing of subtraction operations with right-shifted significand values, and shift estimation circuits to determine estimated left shift amounts for normalizing the difference values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a left shift operation is performed to re-normalize the significand after subtracting two similar floating-point numbers, then the significand is restored to normal form, but significant latency is introduced
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the number of leading zeros in a lookup table before subtraction operations are needed. When subtracting floating-point numbers, the system quickly retrieves the pre-computed leading zero count from the lookup table based on the input significands, avoiding the time-consuming process of actually counting leading zeros during the critical subtraction path. This pre-computation eliminates latency while maintaining normalization accuracy.
Solution Approach 2:
The patent applies preliminary anti-action by using the pre-computed leading zero information to anticipate and prevent the need for costly left shift operations. The system uses the lookup table data to determine the exact normalization shift needed before performing the subtraction, allowing it to prepare correction factors and adjustment values in advance. This prevents the latency that would otherwise occur during and after the subtraction operation.
2Manufacturing precision
If duplicate subtraction operations are performed to ensure correct non-negative results, then accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-determining which subtraction order will yield a non-negative result using the pre-computed leading zero information. The lookup table provides advance knowledge about the relative magnitudes of the input significands, allowing the system to select the correct subtraction order (A-B or B-A) before performing the operation. This eliminates the need for duplicate subtraction operations or post-computation checks, maintaining accuracy while doubling processing speed.
Solution Approach 2:
The patent applies the taking out principle by extracting the magnitude comparison information from the input significands and storing it separately in the lookup table. This extracted information about which significand is larger is separated from the actual subtraction operation, allowing the system to use this pre-extracted knowledge to make immediate decisions about subtraction order without performing redundant calculations. This separation maintains precision while eliminating unnecessary processing steps.
Data Source
AI summary
An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalized difference value.