Floating-Point Conversion Circuit with Single-Adder Rounding
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Solution Overview
Problem
Conventional methods require two adders to convert binary data between a floating-point number and an integer, incorporating rounding and two's complementation, which is inefficient.
Innovation Solution
An apparatus and method that utilize a data converter to determine the sign and output format of binary data, a bias value generator to calculate a bias value based on rounding mode and sticky bits, and an adder to convert the data into a two's complement number, reducing the need for multiple adders by incorporating rounding and two's complementation in a single operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to convert binary data between floating-point and integer formats, then the conversion can be completed, but two separate adders are required which increases device complexity and reduces processing efficiency
Solution Approach 1:
The patent merges the functions of two separate adders into a single adder by combining the rounding operation and two's complementation operation. The adder simultaneously performs addition for rounding and bit inversion for two's complement conversion, reducing the total number of adders from two to one while maintaining conversion accuracy between floating-point and integer formats
Solution Approach 2:
The single adder in the patent is designed to perform multiple functions: it acts as both a rounding adder and a two's complement adder. By controlling the input signals and operation modes, the same hardware component executes different conversion tasks, eliminating the need for dedicated separate adders for each function and thereby reducing device complexity
Data Source
AI summary
An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.