Floating-Point Denormalization Conversion in a Single Clock Cycle

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing floating-point number conversions between formats like binary16 and DLF take longer than one clock cycle without additional hardware, necessitating a more efficient method.

Innovation Solution

A system and method for floating-point conversion with denormalization that uses a lookup table to determine biasing and denormalization constants, allowing for parallel processing of exponent and fraction value conversions within a single clock cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If floating-point conversion is performed using conventional methods, then conversion accuracy is maintained, but conversion time exceeds one clock cycle

Engineering Contradiction:
Improveconversion speedVSAvoidconversion time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores denormalization constants in a lookup table before conversion is needed. When converting floating-point numbers, the system retrieves pre-computed constants based on exponent values, eliminating the need for time-consuming runtime calculations and enabling single-clock-cycle conversion

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conversion process is divided into independent parallel operations: exponent biasing and fraction denormalization are performed simultaneously using separate constant sets. This segmentation allows both operations to complete within one clock cycle without sequential delays

Inventive Principle:
Principle #1Segmentation

2Productivity

If additional hardware is added to enable single-clock-cycle conversion, then conversion speed improves, but device complexity increases

Engineering Contradiction:
Improveconversion throughputVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Denormalization constants are pre-computed and stored in lookup tables during system initialization or manufacturing. This preliminary action transfers computational complexity from runtime hardware operations to pre-processing, allowing simple retrieval operations during actual conversion

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces denormalization constants as intermediary values that mediate between the input floating-point representation and the output format. These constants serve as pre-computed conversion factors that simplify the actual conversion operation to basic arithmetic and lookup operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12585430B2Floating-point conversion with denormalization
Publication Date: 2026.03.24 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12585430B2 patent drawing
  • US12585430B2 patent drawing
  • US12585430B2 patent drawing

AI summary

A method, computer program, and computer system are provided for floating-point conversion with denormalization in a single clock cycle. An input floating-point number corresponding to an input data type is received. An exponent value and a fraction value are extracted from the received input floating-point number. A biasing constant associated with converting the received input floating-point number from the input data type to an output data type is determined. The exponent value is biased based on the biasing constant. The fraction value is converted to the output data type based on a denormalization constant associated with the extracted exponent value and the determined biasing constant. Biasing the exponent value and converting the fraction value occurs in a single clock cycle based on performing these actions in parallel. A floating-point number is output in the output data type corresponding to the converted fraction value and the biased exponent value.