Floating-Point Division Circuitry for Accurate Subnormal Results
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Solution Overview
Problem
Existing floating-point division techniques struggle with subnormal values, particularly in reciprocal implementations, leading to inaccurate results and inefficiencies in graphics applications.
Innovation Solution
A processor architecture that includes hardware for floating-point division operations, utilizing fixed-point unit circuitry to handle subnormal values, which reduces chip area and power consumption while maintaining precision through fast and precise modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If floating-point division is implemented using reciprocal operations, then division speed is improved, but accuracy deteriorates when handling subnormal values
Solution Approach 1:
The patent changes the representation parameter of subnormal values by detecting them and converting to a special format that allows correct reciprocal multiplication. The control circuitry modifies exponent and mantissa parameters to transform subnormal division into a form compatible with reciprocal-based division, resolving the accuracy issue while maintaining speed.
Solution Approach 2:
The patent introduces an intermediary conversion step where subnormal values are transformed into a special intermediate representation before reciprocal multiplication. This intermediary format acts as a bridge between subnormal input and the reciprocal division mechanism, ensuring accurate results without sacrificing the speed advantage of reciprocal operations.
2Measurement precision
If dedicated floating-point division hardware is implemented, then division accuracy is improved, but chip area increases
Solution Approach 1:
The patent makes existing reciprocal multiplication hardware universal by adding subnormal detection and conversion capabilities. The same reciprocal unit that handles normal values is reused for subnormal values through format conversion, eliminating the need for separate dedicated division hardware and reducing chip area while maintaining accuracy.
Solution Approach 2:
The patent merges subnormal value handling into the existing reciprocal multiplication pipeline by integrating detection and conversion logic. Instead of separate hardware paths for normal and subnormal division, the patent combines them into a unified approach that uses the same core computational units, reducing overall chip area.
3Speed
If full hardware floating-point division is implemented, then division speed is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic behavior to the division implementation by detecting the input type (normal vs. subnormal) and adaptively selecting the appropriate processing path. This dynamic approach allows the system to use efficient reciprocal multiplication for most cases while handling subnormal cases specially, optimizing the balance between speed and power consumption based on actual operating conditions.
Solution Approach 2:
The patent dynamically changes parameters such as exponent bias and mantissa formatting based on whether the input is normal or subnormal. This parameter adaptation allows the use of simpler, lower-power reciprocal multiplication hardware for the majority of normal cases while correctly handling subnormal cases through controlled parameter transformations.
Data Source
AI summary
Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.