Floating Polysilicon ESD Protection for Input Pin Reliability
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Solution Overview
Problem
Current integrated circuits face challenges in electrostatic discharge (ESD) protection, particularly at input pins, where reducing transistor breakdown voltages to achieve smaller device sizes is difficult and often increases fabrication complexity with limited effectiveness.
Innovation Solution
The implementation of a system and method using floating and/or biased polysilicon regions to enhance ESD protection, which includes specific transistor configurations and dielectric layers to delay ESD stress current reaching gate regions and increase drain resistance without violating ESD design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD implant is used to adjust breakdown voltages, then ESD protection is improved, but fabrication complexity increases with limited effectiveness
Solution Approach 1:
The patent changes the physical parameters of the transistor structure by introducing polysilicon regions with different work functions and adjusting doping concentrations in the drain region. This modifies the breakdown voltage characteristics without requiring additional fabrication implants, thereby improving ESD protection while avoiding increased fabrication complexity
Solution Approach 2:
The patent employs a composite structure combining polysilicon regions with silicon dioxide dielectric layers and doped semiconductor regions. This composite approach creates tailored electrical fields that enhance breakdown voltage control and ESD protection performance through the synergistic interaction of different materials
2Productivity
If transistor breakdown voltages are reduced to achieve smaller device sizes, then circuit density is improved, but ESD protection effectiveness is limited
Solution Approach 1:
The patent applies local quality modification by introducing polysilicon regions specifically in the drain area of the transistor, rather than uniformly modifying the entire device. This localized approach allows the breakdown voltage to be reduced in specific regions for higher density while maintaining enhanced ESD protection where the polysilicon structures are placed
Solution Approach 2:
The patent addresses the breakdown voltage issue by adding a spatial dimension to the ESD protection mechanism through vertically stacked polysilicon regions and dielectric layers. This three-dimensional structure enables independent control of breakdown characteristics without compromising the planar device footprint, thus achieving both high density and effective ESD protection
Data Source
AI summary
A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.