Floating SiGe Transistor Suppressing Short Channel Effect
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to suppress the short channel effect in transistors while avoiding the high cost and integration difficulties associated with SiGe on insulator (SGOI) substrates, which are expensive and complex to form, and challenging to integrate with silicon substrates.
Innovation Solution
A method for forming a transistor using a silicon substrate, involving the sequential formation of SiGe layers and a silicon layer, with a hard mask layer to expose and remove specific regions, creating a cavity and isolating layer to float the SiGe structure, thereby suppressing the short channel effect without the need for expensive SGOI substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SGOI substrate is used to suppress short channel effect, then transistor performance is improved, but manufacturing cost increases and integration difficulty increases
Solution Approach 1:
The patent divides the substrate into multiple regions with different structures: a first region with a cavity and floating SiGe layer for the transistor channel, and second regions with SiGe layers for contact regions. This segmentation allows the transistor region to benefit from the floating structure that suppresses short channel effect, while contact regions maintain good electrical contact, thus improving transistor performance without requiring a completely expensive SGOI substrate throughout the entire device structure.
Solution Approach 2:
The patent applies different structural configurations to different regions: the first region has a cavity with a floating SiGe layer to suppress short channel effect in the channel area, while the second regions have SiGe layers that provide good electrical contact. This local differentiation allows each region to have the specific properties needed for its function, achieving high transistor performance while avoiding the need to use expensive SGOI substrate everywhere, thus reducing overall manufacturing cost.
2Reliability
If SGOI substrate is used to suppress short channel effect, then transistor performance is improved, but integration with silicon substrates becomes difficult
Solution Approach 1:
The patent implements a localized floating structure only in the first region where the transistor channel is formed, while the second regions maintain direct contact with the silicon substrate. This allows the transistor region to benefit from short channel effect suppression through the floating SiGe layer, while the contact regions maintain compatibility with standard silicon substrate processing and integration, thus resolving the integration difficulty without sacrificing transistor performance.
Solution Approach 2:
The patent uses a selectively formed cavity structure as an intermediary approach: instead of requiring a complete SGOI substrate that is difficult to integrate, the cavity is formed only in the specific region needed for transistor operation. This intermediary structure provides the benefits of floating SiGe layer for short channel effect suppression while maintaining compatibility with standard silicon substrate integration processes in other regions.
3Productivity
If gate length is reduced to increase device density, then operation speed and data storage increase, but short channel effect becomes more severe
Solution Approach 1:
The patent performs preliminary action by forming the cavity and floating SiGe layer structure before fabricating the transistor with reduced gate length. This pre-established floating structure creates a potential well that confines carriers in the channel region, providing inherent suppression of short channel effect. As a result, transistors with shorter gate lengths can be fabricated with reduced leakage current, enabling higher device density and operation speed without suffering from severe short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and improves transistor performance by suppressing the short channel effect, reduces processing costs, and facilitates easy integration with other silicon-based devices, while maintaining the high carrier mobility benefits of SiGe layers.
Implementation Method 1
The SiGe layer of the substrate often provides high carrier mobility and low contact capacitance
Data Source
AI summary
A transistor and a method for forming the transistor are provided. The transistor can be formed over a substrate including a first region and second regions on opposite sides of the first region. On the substrate, a first SiGe layer can be formed, followed by forming a first silicon layer on the first SiGe layer and forming a second SiGe layer on the first silicon layer. The second SiGe layer and the first silicon layer within the second regions are removed. The first silicon layer within the first region is removed to form a cavity such that the second SiGe layer is floated. An isolating layer is formed in the cavity. Second silicon layers are formed in the second regions. A gate structure is formed on the second SiGe layer within the first region and the second silicon layers are doped to form a source and a drain.