Floating Spacer for Gate Electrode Protection in Semiconductor Devices
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Solution Overview
Problem
Current semiconductor device manufacturing techniques face challenges in defining the position of through holes and controlling critical dimensions below 14 nanometers, leading to potential defects and performance issues due to dimensional shifts or dislocated holes in the wiring structure.
Innovation Solution
A semiconductor device is formed with a floating spacer on the sidewall of the gate structure, which has etching selectivity relative to the dielectric layer, assisting in defining the contact opening and protecting the gate electrode, thereby improving accuracy and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional techniques are used to form through holes in dielectric layers, then the wiring structure can be formed, but the position of through holes cannot be defined accurately and critical dimension control fails when CD goes below 14 nanometers
Solution Approach 1:
The floating spacer is formed in advance before the contact hole etching process. This preliminary structure serves as a reference and protection layer, enabling accurate positioning and preventing damage to the gate electrode during subsequent processing steps.
Solution Approach 2:
The floating spacer acts as an intermediary element between the gate structure and the contact hole formation process. It provides a protective barrier that mediates the interaction between etching processes and the gate electrode, preventing direct damage while maintaining positioning accuracy.
2Ease of manufacture
If the dielectric layer height is made less than the gate electrode height to leave portions uncovered, then the floating spacer can be formed on the sidewall, but this creates a more complex structure
Solution Approach 1:
The dielectric layer is segmented in height relative to the gate electrode, creating distinct regions. The uncovered portion allows the floating spacer to be formed on the sidewall, while the covered portion maintains structural support and electrical isolation.
Solution Approach 2:
The solution moves from a two-dimensional planar structure to a three-dimensional structure by forming the floating spacer on the sidewall of the gate electrode. This vertical dimensionality change enables the spacer to serve both as a positioning reference and a protective barrier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The floating spacer effectively protects the gate electrode and enhances the accuracy of the semiconductor device formation by defining the contact opening, addressing the limitations of existing techniques and improving the overall performance of the device.
Implementation Method 1
The floating spacer has an etching selectivity relative to the dielectric layer such that the floating spacer may achieve the purpose of protecting the gate electrode
Data Source
AI summary
A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.