Floating Staircase Word Lines in 3D Non-Volatile Memory
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Solution Overview
Problem
The existing 3D memory devices with staircase word lines face challenges in forming efficient connections between segments across different layers, leading to increased cost and defect density due to complex lithography and etching processes, as well as the stair-interconnection area penalty which encroaches into memory space.
Innovation Solution
The solution involves forming staircase word lines using a sidewall process where segments are decoupled from risers, with risers formed outside the memory cell portion, and using a stairwell structure with conductive sidewalls to connect segments across different memory layers, reducing the number of lithography processes needed and optimizing riser formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex lithography and etching processes are used to form connections between segments across different layers, then connection reliability is improved, but manufacturing cost and defect density increase
Solution Approach 1:
The word line is divided into multiple segments located in different memory layers, with each segment independently formed. The connections between segments are established through conductive plugs and vias, allowing each segment to be processed separately with simpler lithography and etching steps, thereby reducing manufacturing complexity and defect density while maintaining connection reliability
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple memory layers. Word line segments are distributed across different z-height layers, and connections are formed through vertical vias and conductive plugs. This dimensional transition allows segments to be formed in parallel across layers using simpler 2D processes, reducing the complexity of forming inter-layer connections
2Ease of manufacture
If stair-interconnection area is increased to facilitate connections between segments, then ease of connection formation is improved, but memory space is reduced
Solution Approach 1:
Connection structures (vias and conductive plugs) are formed in the vertical dimension by extending conductive materials through vias that penetrate dielectric layers between memory layers. This vertical connection approach eliminates the need for large horizontal stair-interconnection areas, as connections are made through the thickness of the structure rather than across its surface, thereby preserving memory space while facilitating segment interconnections
3Manufacturing precision
If multiple lithography processes are used to form staircase word lines, then manufacturing precision is improved, but productivity is reduced
Solution Approach 1:
The staircase word line structure is segmented into multiple independent word line segments that can be formed in parallel across different memory layers. Each segment uses standard lithography and etching processes, but the segmented architecture allows simultaneous formation of multiple segments, thereby maintaining precision while improving overall production efficiency through parallel processing
Solution Approach 2:
Dielectric layers and conductive plug structures are formed in advance during the memory layer stacking process, before the final word line segment formation. This preliminary preparation of connection structures allows subsequent lithography steps to focus only on defining word line segments, reducing the number of iterative lithography-etch cycles needed and improving productivity
Data Source
AI summary
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.