Floating-Tap DFE Using Shift Registers for PVT-Stable ISI Cancellation
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Solution Overview
Problem
In data communication applications, existing equalization techniques face challenges in accurately compensating for frequency-dependent signal degradation in communications channels due to unknown or varying signal characteristics, leading to inefficiencies in signal transmission and reception.
Innovation Solution
The implementation of a Decision Feedback Equalizer (DFE) with a constrained set of floating-tap positions, using downsampling techniques such as phase pruning and phase amalgamation, to cancel post-cursor ISI while reducing power consumption and circuit complexity, and employing digital shift registers to account for PVT variations without calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of DFE filter taps is increased to cancel more ISI terms, then the ISI cancellation performance is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts and processes only the most significant post-cursor ISI terms using a selective approach. By identifying and canceling only the dominant ISI components rather than all possible terms, the system achieves effective ISI cancellation with reduced filter complexity and lower power consumption compared to traditional approaches that process all taps uniformly
Solution Approach 2:
The patent applies different processing quality to different tap positions. Rather than uniformly processing all DFE taps with the same complexity, the system applies higher processing precision to taps with significant ISI impact while using simpler processing for taps with minimal impact, optimizing the balance between performance and complexity
2Reliability
If the number of DFE filter taps is increased to cancel more ISI terms, then the ISI cancellation performance is improved, but the power consumption increases
Solution Approach 1:
The patent extracts and processes only the most significant post-cursor ISI terms using a selective approach. By identifying and canceling only the dominant ISI components rather than all possible terms, the system achieves effective ISI cancellation with reduced filter complexity and lower power consumption compared to traditional approaches that process all taps uniformly
Solution Approach 2:
The patent implements partial action by processing only the necessary portion of ISI terms that have significant impact on performance. Rather than exhaustively processing all possible tap positions, the system identifies and processes only the critical taps, reducing computational load and power consumption while maintaining adequate ISI cancellation performance
3Adaptability or versatility
If analog delay elements are used in floating tap DFE, then the floating tap functionality is achieved, but calibration is required which increases complexity and time
Solution Approach 1:
The patent replaces analog delay elements with digital delay implementation using shift registers. This substitution eliminates the need for complex analog calibration procedures while maintaining the floating tap functionality, as digital delays can be precisely controlled and adjusted without calibration
Solution Approach 2:
The patent implements self-calibration capability where the system automatically adjusts its delay elements without requiring external calibration equipment or procedures. The digital implementation allows the system to self-adjust delay values based on operational conditions, eliminating manual calibration complexity
4Productivity
If high clock rates are used in DFE to process all tap positions, then the processing speed is improved, but the power consumption and complexity increase
Solution Approach 1:
The patent implements partial action by processing only the necessary portion of ISI terms that have significant impact on performance. Rather than exhaustively processing all possible tap positions at high clock rates, the system identifies and processes only the critical taps, reducing computational load and power consumption while maintaining adequate ISI cancellation performance
Data Source
AI summary
Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.