Floating Top Plate Isolator Stack for High-Voltage Isolation
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Solution Overview
Problem
Existing galvanic isolators face challenges in achieving high voltage isolation and reducing parasitic capacitance, which limits their performance in applications requiring high isolation voltages, such as industrial and medical settings, where they often struggle to handle surge events and maintain effective isolation across different voltage domains.
Innovation Solution
A monolithic integrated isolator device with a back-to-back configuration on a single silicon substrate, where top isolator components are floated and connected in series, reducing parasitic capacitance by increasing the thickness of dielectric material between them and the underlying conductor, and using a smaller lateral area for top isolator components to shield them from the substrate, thereby enhancing voltage capabilities and isolation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple isolators are connected in series to achieve higher isolation voltage, then the isolation voltage capability is improved, but the device complexity and footprint increase
Solution Approach 1:
The patent combines multiple isolator components (first isolator component, second isolator component, third isolator component, and fourth isolator component) onto a single monolithic substrate, integrating what would traditionally require separate devices into one unified structure. This merging achieves the cumulative isolation properties of multiple isolators while maintaining a smaller footprint and reducing overall device complexity.
Solution Approach 2:
The patent implements a nested arrangement where isolator components are positioned in overlapping vertical layers. The first and second isolator components are positioned over the substrate, while the third and fourth isolator components are positioned over the first and second isolator components respectively. This nesting allows multiple isolators to occupy overlapping spatial regions, achieving high isolation voltage without proportionally increasing the device footprint.
2Reliability
If multiple isolators are connected in series to achieve higher isolation voltage, then the isolation voltage capability is improved, but the area occupied increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional vertical stacking configuration. Isolator components are arranged in multiple vertical layers with overlapping horizontal projections. The third and fourth isolator components are positioned over the first and second isolator components, utilizing the vertical dimension to achieve cumulative isolation properties without proportionally increasing the horizontal footprint.
3Ease of manufacture
If top isolator components are connected to underlying conductors, then manufacturing is simplified, but parasitic capacitance increases reducing isolation performance
Solution Approach 1:
The patent extracts the top isolator components (third and fourth isolator components) from direct electrical connection to the substrate and underlying conductors. These components are positioned over the first and second isolator components without direct contact to underlying conductors, thereby eliminating parasitic capacitance pathways while maintaining manufacturability through the integrated substrate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher isolation voltages, reduced parasitic capacitance, and cost-effectiveness by maintaining the cumulative isolation properties of multiple isolators in a smaller footprint, suitable for high-voltage applications, while ensuring robustness against surge events and voltage imbalances.
Implementation Method 1
increasing the thickness of dielectric material between them and the underlying conductor
Implementation Method 2
using a smaller lateral area for top isolator components to shield them from the substrate
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single monolithic substrate are connect in series to achieve a higher amount of electrical isolation for a single substrate than for one of the isolators alone. A pair of isolators in the back-to-back configuration have top and bottom isolator components where the top isolator components are connected together and electrically isolated from the underlying substrate, resulting in floating top isolator components. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.