Floating Transistor Interconnect Layout for Lower Parasitic Coupling
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Solution Overview
Problem
As integrated circuit elements decrease in size, connecting them becomes challenging due to non-scaling conductive interconnects, leading to higher parasitic couplings and resistance issues, particularly in connecting lower level terminals of transistors.
Innovation Solution
The use of three-dimensional electrically conductive interconnects with metals of lower resistance, combined with the introduction of floating transistors that have unconnected drain, source, and gate regions, allows for simplified routing and reduced parasitic capacitance, enabling efficient connection of circuit transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size of integrated circuit elements is reduced to increase functionality, then more elements can be incorporated into the chip, but conductive interconnect does not scale proportionally leading to higher parasitic couplings and resistance
Solution Approach 1:
The patent introduces floating transistors as dummy structures in alternating positions within the transistor array, creating a three-dimensional routing architecture. This allows interconnect wires to be routed over the floating transistor regions, effectively adding a vertical dimension to the interconnect path and reducing parasitic couplings between adjacent active transistors.
Solution Approach 2:
Floating transistors serve as intermediary structures that mediate between the scaling-down pressure on feature size and the need to maintain low parasitic couplings. These dummy transistors with unconnected terminals act as buffer elements, providing routing space and electrical isolation without consuming functional transistor resources.
2Device complexity
If conventional interconnect routing is used for scaled-down transistors, then layout simplicity is maintained, but parasitic capacitance and resistance increase
Solution Approach 1:
The transistor array is segmented into alternating rows or columns of active transistors and floating transistors. This segmentation creates distinct routing regions where interconnect can be placed over floating transistor areas, reducing capacitive coupling between adjacent active transistors while maintaining a regular, manufacturable layout pattern.
Solution Approach 2:
The patent changes the electrical state of certain transistor terminals by leaving them unconnected (floating), thereby transforming them from active functional elements to passive routing aids. This parameter change in terminal connectivity enables the same physical structure to serve dual purposes: maintaining layout regularity while reducing parasitic effects.
3Object-affected harmful factors
If floating transistors with unconnected terminals are introduced, then parasitic capacitance is reduced and routing is simplified, but device structure complexity increases
Solution Approach 1:
The floating transistors, while structurally similar to active transistors, serve multiple functions: they provide routing space for interconnect, act as electrical shields to reduce parasitic coupling, and maintain the regular alternating pattern required for manufacturability. This multi-functionality justifies the increased structural complexity.
Solution Approach 2:
The floating transistors are essentially copies of active transistors in terms of physical structure (gate, source, drain regions), but with the key difference that their terminals are not connected to functional circuits. This copying approach allows the same fabrication processes to be used while creating elements with different electrical characteristics for routing purposes.
Data Source
AI summary
An electronic circuit includes multiple field effect transistors (FETs). The multiple FETs include multiple circuit transistors having drain and source regions connected to circuits, and multiple floating transistors having unconnected and floating drain, source, and gate regions. The multiple circuit transistors are alternatingly arranged with the multiple floating transistors so that a circuit transistor is arranged adjacent to a floating transistor, and at least a portion of electrically conductive interconnect connected to the circuit transistors is arranged over the drain and source regions of the floating transistors.