Floating Via Cell Deck Layout for 3D Memory Protection
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to increase integration density while minimizing manufacturing defects, particularly in three-dimensional memory devices where memory cells are prone to damage during processing, leading to defects and reduced device functionality.
Innovation Solution
Incorporating floating vias within the cell deck, which provide mechanical support and protection to memory cells during manufacturing, especially during the chemical-mechanical polishing process, by being electrically isolated and distributed throughout the deck to maintain via density and prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked to increase integration density, then integration density is improved, but manufacturing defects increase due to damage during processing
Solution Approach 1:
The patent applies preliminary action by forming protective cap structures and sacrificial material layers before the memory cells are fully fabricated and stacked. These protective features are prepared in advance to prevent damage during subsequent manufacturing processes such as chemical-mechanical polishing and mask removal, thereby resolving the contradiction between high integration density and manufacturing reliability
2Manufacturing precision
If chemical-mechanical polishing is used to remove mask material, then manufacturing precision is improved, but memory cells suffer mechanical damage
Solution Approach 1:
The patent implements beforehand cushioning by forming cap structures over the memory cells and introducing sacrificial material layers before the chemical-mechanical polishing process. These protective features absorb mechanical stress and prevent direct contact between the polishing tools and the memory cells, thereby maintaining manufacturing precision while preventing mechanical damage
3Reliability
If via density is increased to improve device functionality, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by designing the cap structures and sacrificial material layers to serve multiple functions simultaneously: they protect memory cells during manufacturing, maintain via density distribution, and facilitate mask removal. This multi-functionality allows high via density to be achieved without proportionally increasing manufacturing complexity, as the same structures provide both protection and process control
Data Source
AI summary
A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.