Floating Voltage Source LDO for Low Dropout Regulation

The patent introduces a floating voltage source that adds a voltage offset dimension to the opamp output, allowing the gate voltage to be elevated above the supply voltage. This dimensional change in voltage control enables the nMOS transistor to operate with lower Vds while maintaining proper gate control, thereby reducing dropout voltage while keeping the output transistor type.

The patent changes the operating parameters of the nMOS transistor through the floating voltage source, enabling it to achieve low dropout voltage performance similar to pMOS transistors. By elevating the gate voltage above the supply voltage, the nMOS transistor operates in an optimized region that provides both low dropout voltage and maintains low output impedance across frequency, eliminating the need for large external capacitors.

The patent uses the floating voltage source as an intermediary between the opamp and the output transistor gate. The opamp maintains its excellent constant voltage control and low ripple characteristics, while the floating voltage source adds the necessary voltage offset to achieve low dropout. This intermediary approach combines the advantages of both opamp control and low dropout performance without the ripple issues of charge pumps.

The patent implements dynamic operation by introducing switching elements that can rapidly transition the LDO between active regulation mode and power-down mode. The floating voltage source and switching mechanism enable the circuit to maintain voltage regulation when needed while completely shutting down power consumption during idle periods, adapting to the time-slot based operation requirements of modern electronic systems.