Floating Well ESD Protection for Low Parasitic Capacitance
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Solution Overview
Problem
FinFET transistors used in ESD protection circuits are susceptible to damage from high ESD currents, leading to overheating and malfunction, and existing ESD protection structures have high parasitic capacitance that degrades high-frequency signal performance.
Innovation Solution
The implementation of an ESD protection circuit with floating wells and a series chain of capacitors during normal operation, which acts like a large PN diode during ESD events, reducing parasitic capacitance and enhancing high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If FinFET transistors are used in ESD protection circuits, then device area is reduced and leakage is lowered, but the transistors become susceptible to damage from high ESD currents causing overheating and malfunction
Solution Approach 1:
The ESD protection circuit is segmented into multiple series-connected transistor stages (e.g., three FinFET transistors in series). This segmentation distributes the ESD current stress across multiple devices rather than concentrating it in a single transistor, reducing the current density and heat generation in each individual device while maintaining effective ESD protection.
Solution Approach 2:
Isolation structures (such as oxide layers or dummy transistors) are introduced as intermediary elements between the FinFET transistors. These intermediaries provide thermal isolation and electrical isolation, preventing direct heat transfer between adjacent transistors and reducing the risk of thermal runaway while maintaining the compact FinFET structure.
2Reliability
If traditional ESD protection structures are used, then ESD protection is provided, but parasitic capacitance is high which degrades high-frequency signal performance
Solution Approach 1:
The invention changes the structural parameters of the ESD protection circuit by using FinFET transistors with specific dimensional characteristics (smaller channel length, controlled width) and configuring them in series. This parameter optimization reduces the parasitic capacitance compared to traditional planar structures while maintaining adequate ESD protection capability through the series configuration that limits discharge current.
3Use of energy by moving object
If smaller transistors are used in the core, then power consumption is reduced and less heat is produced, but the transistors become much more susceptible to over-voltage failure
Solution Approach 1:
ESD protection circuits are placed in the periphery of the IC design, acting as preliminary protective barriers before ESD pulses can reach the sensitive core transistors. This preliminary action intercepts and shunts dangerous ESD currents away from the low-voltage core circuitry, allowing the use of smaller, lower-power transistors in the core without compromising their vulnerability to over-voltage damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects FinFET transistors from ESD damage while minimizing parasitic capacitance, thereby improving high-speed performance and preventing overheating.
Implementation Method 1
existing ESD protection structures have high parasitic capacitance that degrades high-frequency signal performance
Implementation Method 2
Integrated circuits (IC's) are prone to damage and failure caused by an electro-static-discharge (ESD) pulse
Implementation Method 3
FinFET transistors used in ESD protection circuits are susceptible to damage from high ESD currents, leading to overheating and malfunction
Data Source
AI summary
An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.