Floating Well Memory Devices for Bulk CMOS Cost Reduction
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Solution Overview
Problem
The standard manufacturing process for semiconductor devices is cost-efficient but struggles to shrink memory cell size, leading to high manufacturing costs and space requirements, especially in system-on-a-chip applications, and often necessitates proprietary processes that increase the entry barrier.
Innovation Solution
The development of semiconductor devices with deeper trench isolation regions that create floating wells capable of holding charge, allowing information storage and manufactured using standard logic processes, enabling cost-efficient and power-effective memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard process manufacturing is used for memory devices, then manufacturing cost is reduced, but device area and space requirements increase
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional vertically-aligned memory structures. Memory holes are formed vertically through the substrate, and bit lines are positioned at different vertical levels, enabling memory storage in the vertical dimension rather than only in the planar area, thus reducing the footprint area while maintaining compatibility with standard CMOS processing
Solution Approach 2:
The patent implements a nested structure where memory holes containing charge storage regions are positioned within and between device regions. The memory holes are vertically nested within the substrate thickness, and bit lines are nested at different vertical levels, allowing multiple memory elements to be stacked vertically within a small planar footprint
2Ease of manufacture
If standard process manufacturing is used for memory devices, then ease of manufacture is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory structure into distinct vertical components: shallow trenches for device isolation, deep trenches for memory hole formation, charge storage regions within the memory holes, and vertically-stacked bit lines at different levels. This segmentation allows each component to be formed using separate, well-defined process steps within the standard CMOS manufacturing sequence, managing complexity through modular construction
Solution Approach 2:
The patent resolves structural complexity by moving memory formation into the vertical dimension. Instead of complex planar arrangements, memory holes are formed vertically through the substrate, and bit lines are positioned at different vertical levels, simplifying the manufacturing process while achieving high-density memory storage
3Reliability
If proprietary manufacturing processes are used for memory devices, then memory device performance is improved, but manufacturing cost and entry barrier increase
Solution Approach 1:
The patent creates a universal memory structure that can be manufactured using standard CMOS processing techniques already widely available in the industry. The same fabrication processes used for logic devices are adapted to form memory structures, eliminating the need for proprietary or specialized manufacturing equipment and processes, thereby reducing manufacturing costs and lowering the entry barrier while maintaining reliable memory performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of memory devices that are cost-efficient in both manufacturing and power consumption, while being scalable and compatible with existing standard processes, reducing the need for proprietary foundries and minimizing space requirements.
Implementation Method 1
deeper trench isolation regions that create floating wells capable of holding charge
Data Source
AI summary
The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one or more devices to create storage regions (floating wells) that is capable of holding a charge. Depending on the charge in the storage region (floating well), it can represent information. The semiconductor devices of the present invention can be manufactured using the standard process of manufacturing (bulk cmos processing).