Floating-Well MOS Varactor Structure for Higher Tuning Ratio

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current MOS varactors have limitations in tuning ratio and frequency tuning range due to constraints in capacitance variation with voltage, which affects their performance in applications like voltage-controlled oscillators and phase locked loops.

Innovation Solution

A method of forming varactors with a dielectric layer between the substrate and source/drain features, electrically floating the well region to reduce both maximum and minimum capacitance, thereby increasing the tuning ratio and frequency tuning range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional MOS varactor structure is used, then the device can be manufactured with standard processes, but the tuning ratio and frequency tuning range are limited

Engineering Contradiction:
Improvetuning ratioVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The device is divided into two separate regions: a first region containing the varactor structure and a second region containing the doped well region. This segmentation allows the varactor to operate with an electrically floating well, enabling greater capacitance modulation range while maintaining manufacturing compatibility through standard fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulator layer is introduced as an intermediary between the source/drain features and the doped well region. This insulator electrically isolates the well region, creating the floating well effect that enables enhanced tuning ratio without requiring complex process modifications

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the well region is electrically floating, then both maximum and minimum capacitance are reduced increasing tuning ratio, but the device structure becomes more complex

Engineering Contradiction:
Improvefrequency tuning rangeVSAvoidcapacitance management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The insulator is selectively placed only in the second region beneath the source/drain features, creating local electrical isolation. This localized modification achieves the floating well effect precisely where needed for capacitance modulation, without requiring global structural changes that would increase overall device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in a varactor with enhanced tuning ratio and frequency tuning range, improving performance in tunable circuits by effectively managing capacitance variation with voltage.

Implementation Method 1

MOS (metal-oxide-semiconductor) varactors are semiconductor devices that have a capacitance varying as a function of an applied voltage

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

A dielectric layer is formed between the substrate and the source/drain features, thereby blocking a current path

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS20250015159A1Varactors having increased tuning ratio
Publication Date: 2025.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250015159A1 patent drawing
  • US20250015159A1 patent drawing
  • US20250015159A1 patent drawing

AI summary

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.