Floating-Well MOS Varactor Structure for Higher Tuning Ratio

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Solution Overview

Problem

Existing MOS varactors in semiconductor circuits have limited tuning ratios, which affect the frequency tuning range and efficiency of devices such as voltage-controlled oscillators and phase shifters.

Innovation Solution

The formation of varactors with an electrically floating well region by introducing an insulation layer between the substrate and source/drain features, reducing minimum capacitance more than maximum capacitance, thereby increasing the tuning ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an insulation layer is introduced between the substrate and source/drain features to create an electrically floating well region, then the tuning ratio is increased, but the device complexity increases

Engineering Contradiction:
Improvetuning ratioVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

An insulation layer is introduced as an intermediary element between the substrate and source/drain features. This insulation layer creates an electrically floating well region that reduces the minimum capacitance more than the maximum capacitance, thereby increasing the tuning ratio of the varactor device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical state of the well region from grounded to floating by introducing the insulation layer. This parameter change in the well region's electrical connection status enables differential reduction of capacitance values, specifically reducing Cmin more than Cmax, which increases the tuning ratio.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the minimum capacitance is reduced more than the maximum capacitance to increase tuning ratio, then the frequency tuning range is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvefrequency tuning rangeVSAvoidmanufacturing precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The invention achieves differential capacitance reduction by changing the electrical configuration of the well region. The insulation layer creates a floating well that selectively reduces minimum capacitance more than maximum capacitance, enabling expanded frequency tuning range while maintaining manufacturability through standard insulation layer deposition processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the frequency tuning range of varactors by improving the tuning ratio, providing better performance in voltage-controlled oscillators and phase shifters.

Implementation Method 1

a dielectric layer is formed between the substrate and the source/drain feature, thereby blocking a current path between the source/drain feature and the well region formed in the substrate to set the well region to be electrically floating

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

MOS (metal-oxide-semiconductor) varactors are semiconductor devices that have a capacitance varying as a function of an applied voltage

Methodology Applied
Scientific EffectCapacitance modulation: Capacitance

Data Source

PatentUS20250359080A1Varactors having increased tuning ratio
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250359080A1 patent drawing
  • US20250359080A1 patent drawing
  • US20250359080A1 patent drawing

AI summary

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.