Floor Planning Tool for Integrated Circuit Timing Visualization

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Solution Overview

Problem

The process of designing integrated circuits is hindered by the lack of clear visualization of how block movements affect timing, leading to trial and error experimentation, which wastes resources and delays schedules due to textual timing reports and the complexity of floorplan adjustments.

Innovation Solution

A floor planning tool that provides real-time visualization of timing and space constraints, allowing designers to optimize initial macro/object placement and simplify chip designs by removing combinational logic, thereby enabling efficient identification of common nodes and extended timing paths, and facilitating better utilization of chip space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If blocks are moved around to address gate growth or floorplan needs, then layout flexibility is improved, but timing performance deteriorates

Engineering Contradiction:
Improvelayout flexibilityVSAvoidtiming performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary timing impact analysis before blocks are moved, identifying which timing paths will be affected by proposed layout changes. This allows designers to anticipate timing violations and adjust the floorplan accordingly, preventing timing performance deterioration while maintaining layout flexibility.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system provides real-time feedback on timing impact when blocks are moved, showing designers immediately how layout changes affect timing performance. This feedback loop enables iterative optimization where designers can make small adjustments and see the timing consequences, balancing layout flexibility with timing reliability.

Inventive Principle:
Principle #23Feedback

2Loss of information

If detailed analysis of timing reports is performed, then timing impact understanding is improved, but engineering time and resource usage increase

Engineering Contradiction:
Improvetiming impact understandingVSAvoidengineering time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The system uses color-coded visual indicators to represent different timing impact levels, with colors ranging from green (no impact) to red (severe impact). This visual encoding allows designers to quickly understand timing impacts without reading detailed textual reports, significantly reducing the time required to analyze timing changes while maintaining comprehensive understanding.

Inventive Principle:
Principle #32Color changes

Solution Approach 2:

The system transforms one-dimensional textual timing reports into two-dimensional visual displays showing timing paths, affected blocks, and impact magnitudes in a graphical interface. This dimensional transformation makes timing information more intuitive and easier to comprehend at a glance, reducing the engineering time needed for analysis.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If trial and error experimentation of various floorplans is performed, then optimal layout is improved, but machine resource use and schedule time increase

Engineering Contradiction:
Improveoptimal layoutVSAvoidschedule efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The system performs preliminary evaluation of potential floorplan variations by predicting timing impacts before full implementation. This allows designers to eliminate poor layout options early in the design process, reducing the number of trial and error iterations needed to achieve optimal layout and thereby improving schedule efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system creates simplified visual models or copies of timing paths and layout configurations that can be quickly analyzed and compared. Instead of performing full timing analysis on every floorplan variation, designers can use these visual copies to rapidly evaluate multiple layout options, reducing machine resource consumption while still identifying optimal layouts.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9436796B2Method and apparatus for determining common node logical connectivity
Publication Date: 2016.09.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9436796B2 patent drawing
  • US9436796B2 patent drawing
  • US9436796B2 patent drawing

AI summary

A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.