Floorsweeping Module for Bypassing Defective Cache Memory
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Solution Overview
Problem
The increasing complexity and decreasing feature size in semiconductor manufacturing lead to higher manufacturing defects in integrated circuits, reducing yield and increasing production costs, as defects can render entire circuits non-functional.
Innovation Solution
The implementation of a floorsweeping module that allows selection between multiple cache memory units based on defect indicators, such as production fuses, to bypass or disable defective units, maintaining functionality and external memory interface size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor manufacturing continues with increasing complexity and decreasing feature size, then manufacturing capability and integration density improve, but manufacturing defects increase and yield decreases
Solution Approach 1:
The memory system is divided into multiple independent memory clusters (first memory cluster, second memory cluster), each with its own defect status. The floorsweeping module segments the memory access paths and can independently select functional clusters, allowing defective portions to be isolated and bypassed while maintaining overall system functionality.
Solution Approach 2:
The system dynamically changes the operational parameters by adjusting which memory clusters are active based on defect indicators. The floorsweeping module modifies the selection of memory clusters in response to detected defects, changing the system's operational state to maintain performance despite manufacturing variations.
2Reliability
If defective memory units are bypassed using traditional methods, then functionality is restored, but external memory interface bandwidth and performance are reduced
Solution Approach 1:
The floorsweeping module implements dynamic selection of memory clusters based on real-time defect detection. The system can adaptively switch between different memory cluster configurations to maintain optimal bandwidth, rather than using static bypass methods that permanently reduce performance.
Solution Approach 2:
The floorsweeping module serves multiple functions: it detects defects, selects functional memory clusters, and maintains interface bandwidth. The parallel memory cluster architecture provides universal access paths that can route through different clusters depending on their functional status, preserving full interface capability.
3Adaptability or versatility
If multiple parallel memory clusters are implemented to provide redundancy, then defect bypass capability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The defect indicators (such as production fuses) are pre-configured during manufacturing to identify defective memory clusters before the product reaches the customer. The floorsweeping module uses these pre-established indicators to quickly determine which clusters are functional, eliminating the need for complex runtime defect detection and simplifying the bypass logic.
4Measurement precision
If production fuses are used as defect indicators, then defect detection precision improves, but manufacturing process complexity increases
Solution Approach 1:
The production fuse system is integrated into the existing semiconductor manufacturing process, using standard fuse blowing techniques that are already part of the fabrication workflow. The defect indicators are self-configured during manufacturing without requiring additional external testing or configuration steps, maintaining ease of manufacture while providing precise defect detection.
Data Source
AI summary
An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.