Daisy-Chained Flop Power Switch Ramping for Noise Control
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Solution Overview
Problem
Integrated circuits face challenges in managing power consumption and minimizing noise on power supply connections due to leakage currents, especially in high-performance devices, which affects operational accuracy and requires balancing delay and noise considerations across varying process, voltage, and temperature conditions.
Innovation Solution
The implementation of a power manager circuit that generates block enables and a block enable clock, staggering power switch enables over multiple clock cycles to control current flow changes and set the clock frequency independently of process, voltage, and temperature conditions, using series-connected flops to manage power gated blocks and reduce the rate of current change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is implemented to reduce leakage current, then power consumption is reduced, but noise on power supply connections increases due to rapid current changes
Solution Approach 1:
The patent applies periodic action by using a block enable clock to rhythmically control the enabling of power switches in a staged manner. Instead of enabling all power switches simultaneously, the clock signal distributes enable signals across multiple clock cycles, creating a periodic, controlled current ramp-up that reduces noise while maintaining power gating benefits.
Solution Approach 2:
The patent segments the power switching operation by dividing the enable signal distribution across multiple clock cycles. Each clock cycle enables a portion of the power switches rather than all at once, segmenting the total current change into smaller, manageable increments that reduce power supply noise.
2Productivity
If the rate of change of current is increased to reduce enable delay, then productivity improves, but noise on power supply connections increases
Solution Approach 1:
The block enable clock creates a periodic rhythm for enabling power switches, where the clock frequency is specifically chosen to balance the rate of current change. This periodic control allows the system to achieve acceptable enable speeds while maintaining controlled current ramps that minimize noise generation.
Solution Approach 2:
The patent changes the parameter of current change rate by controlling it through a clocked mechanism rather than allowing uncontrolled rapid transitions. The clock frequency and duty cycle are adjusted to optimize the balance between enable speed and noise generation, transforming the parameter from uncontrolled to precisely managed.
3Productivity
If clock frequency is set high to reduce enable time, then productivity improves, but process, voltage, and temperature variations cause unreliable operation
Solution Approach 1:
By using a periodic clock signal with a conservatively chosen frequency, the system ensures that each clock cycle provides sufficient time for power switch enabling across all process, voltage, and temperature conditions. The periodic nature allows timing to be predictable and reliable while still achieving acceptable enable speeds.
Solution Approach 2:
The system performs preliminary timing analysis to determine a clock frequency that works reliably across all PVT conditions before implementation. This preliminary action ensures that the chosen clock frequency provides adequate timing margin, preventing reliability issues while maintaining acceptable performance.
Data Source
AI summary
In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.