Flow Cache Stale Memory Address Detection via Learn Index Validation
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Solution Overview
Problem
In computer networks, the reliance on flow caches for packet forwarding can lead to incorrect processing due to asynchronously freed memory addresses, especially as the number of flows increases, resulting in higher refresh times and potential network device failures.
Innovation Solution
Implementing a memory address map with learn indexes to validate memory addresses before processing, ensuring that stale addresses are identified and invalidated, and packets are forwarded using the forwarding subsystem to prevent crashes and improve scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flow cache is used for packet forwarding, then forwarding speed is improved, but memory address staleness causes incorrect processing and device failures
Solution Approach 1:
The patent implements a feedback mechanism where the forwarding subsystem monitors memory address allocations and notifications are sent back to the flow cache. When memory is reallocated or freed, the flow cache receives notification and invalidates corresponding entries, ensuring forwarding correctness while maintaining speed benefits.
Solution Approach 2:
The patent introduces a memory address map as an intermediary structure that tracks the relationship between memory addresses and flow cache entries. This mediator enables the system to detect stale references without requiring continuous synchronization between the flow cache and forwarding subsystem.
2Quantity of substance
If the number of flows increases, then network capacity is improved, but refresh time increases and device failures occur
Solution Approach 1:
The patent performs preliminary validation by checking the memory address map before processing packets in the flow cache. This advance check prevents stale memory address usage without requiring periodic full refreshes of the flow cache, enabling the system to handle more flows with reduced refresh overhead.
3Device complexity
If flow cache entries are maintained without validation, then device complexity is reduced, but stale memory addresses cause crashes
Solution Approach 1:
The memory address map serves as a lightweight intermediary validation structure that adds minimal complexity to the flow cache. It provides the necessary reliability check by tracking memory address validity without requiring complex synchronization protocols or redundant cache structures.
Data Source
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AI summary
An example network device includes a flow cache configured to store a flow cache entry that indicates a memory address referenced by one or more actions of the flow cache entry and a first learn index for the memory address, a memory address map configured to store a second learn index for the memory address, and one or more processors implemented in circuity. The network device is configured to receive a packet for the flow and obtain, from the flow cache entry for the flow, the memory address referenced by the one or more actions and the first learn index. The network device is further configured to determine the first learn index matches the second learn index and forward, in response to the determining, the packet using the one or more actions of the flow cache entry.