Flow Cache Bandwidth Utilization via Valid Split Table
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Solution Overview
Problem
The existing network traffic management apparatuses face limitations in flow cache bandwidth utilization due to bandwidth-intensive scrubber processes and invalid entry retrievals, which hinder packet throughput and response times.
Innovation Solution
The implementation of a valid split table and a recently hit split table within the network traffic management apparatus to determine validity and recent usage of flow cache table entries, reducing unnecessary reads and freeing up bandwidth for packet-driven lookups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the configurable hardware logic periodically traverses each entry of the flow cache table to determine whether entries should be evicted or removed, then the flow cache table can be optimized to maintain valid entries, but the scrubber process consumes significant flow cache bandwidth and limits throughput of packet-driven lookups
Solution Approach 1:
The patent divides the flow cache table into multiple segments or sets, allowing the scrubber process to traverse only a subset of entries periodically rather than all entries. This segmentation reduces the bandwidth consumption of the scrubber process while still maintaining validity of entries through distributed traversal across multiple periods.
Solution Approach 2:
The patent implements preliminary validation mechanisms where entries are marked as valid or invalid before the scrubber process needs to traverse them. This allows the scrubber to skip over clearly valid entries, reducing unnecessary bandwidth consumption while maintaining entry validity through pre-established validation states.
2Loss of time
If the scrubber process sequentially reads each entry of the flow cache table at a predefined interval, then entries can be updated with age values and evicted when appropriate, but this process utilizes flow cache bandwidth that could be used for packet-driven lookups
Solution Approach 1:
The patent implements periodic action by having the scrubber process traverse different subsets of flow cache table entries at different time intervals rather than traversing all entries at every interval. This distributes the traversal load over time, maintaining accurate age tracking for entries that need it while reducing overall bandwidth consumption.
Solution Approach 2:
The patent applies local quality by treating different entries in the flow cache table differently based on their characteristics. Entries that are frequently accessed or recently created may not require periodic age updates, while older or less frequently accessed entries do. This selective approach maintains necessary age tracking accuracy while minimizing bandwidth usage.
3Speed
If the configurable hardware logic performs read operations on the flow cache table for every packet transformation lookup, then packet throughput can be maintained, but the bandwidth-intensive scrubber processes and invalid entry retrievals hinder throughput and response times
Solution Approach 1:
The patent implements preliminary action by pre-marking entries as valid or invalid and organizing the flow cache table structure before lookup operations occur. This allows the configurable hardware logic to quickly determine whether an entry is valid without performing full read operations, reducing bandwidth consumption while maintaining packet processing speed.
Solution Approach 2:
The patent extracts the validity determination function from the full entry read operation. By separating the validity check from the complete entry retrieval, the system can quickly determine if an entry is valid and only perform full reads when necessary, reducing overall bandwidth consumption while maintaining processing speed for valid entries.
Data Source
AI summary
A network traffic management apparatus includes a first memory including a flow cache table including a plurality of entries. The network traffic management apparatus further includes configurable hardware logic coupled to the first memory and a processor, the configurable hardware logic including a valid split table including a plurality of entries, wherein each of the plurality of entries includes a validity bit. The configurable hardware logic is configured to implement periodically determining whether the validity bit of each of the valid split table entries is set. Additionally, the configurable hardware logic is further configured to implement retrieving one of the plurality of flow cache table entries corresponding to an index value associated with one of the valid split table entries, when it is determined that the validity bit of the one of the valid split table entries is set.