Variable Latency Flow Control via Identifier Synchronization

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Solution Overview

Problem

In packet communication systems with variable latency, senders face challenges in accurately determining the buffer space available at receivers, leading to potential overflows or underflows due to uncertainties in flow control data synchronization, especially when senders need to estimate buffer capacity and manage XON/XOFF states across long and variable latency interfaces.

Innovation Solution

Incorporating a flow control identifier into packet headers transmitted between sender and receiver devices, allowing for synchronization of buffer states by comparing sent and received identifiers, and using forced flow control instructions to manage buffer states proactively, ensuring accurate flow control and preventing buffer overflows or underflows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If flow control data is transferred over a variable latency interface, then data transmission can occur, but the sender cannot accurately determine buffer space availability leading to overflows or underflows

Engineering Contradiction:
Improvedata transmission rateVSAvoidflow control accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the receiver sends flow control data back to the sender, and the sender tracks the latency of this feedback. By monitoring how long it takes for flow control acknowledgments to return, the sender can dynamically adjust its transmission rate and buffer usage estimates, resolving the contradiction between maintaining high productivity and ensuring flow control reliability in variable latency environments.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by having the sender proactively estimate receiver buffer availability based on historical latency data before transmitting packets. This allows the sender to adjust its transmission behavior in advance, preventing buffer overflows before they occur while maximizing data transmission productivity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the CPU estimates buffer capacity to prevent overflow, then packet loss is reduced, but the CPU must enter XOFF state prematurely due to long latencies

Engineering Contradiction:
Improvebuffer overflow preventionVSAvoidtransmitter utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamics by making the XOFF/XON state transitions adaptive rather than static. The sender dynamically adjusts its buffer capacity estimates based on actual latency measurements and receiver feedback, allowing it to remain in the transmitting state longer when conditions permit while still preventing overflows. This resolves the contradiction by making the system responsive to actual buffer availability rather than relying on conservative fixed estimates.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If shared busses are used to connect data path elements, then system complexity is reduced, but latency becomes long and variable making buffer state tracking difficult

Engineering Contradiction:
Improvedata path structureVSAvoidbuffer state determination
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent uses feedback to compensate for the imprecision introduced by shared busses. By continuously measuring the latency of flow control data returning over the shared bus and using this information to update buffer state estimates, the system achieves accurate buffer state determination despite the variable latency inherent in shared bus architectures.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8199648B2Flow control in a variable latency system
Publication Date: 2012.06.12 CISCO TECHNOLOGY INC
  • US8199648B2 patent drawing
  • US8199648B2 patent drawing
  • US8199648B2 patent drawing

AI summary

A device and method for packet flow control is described. The method may comprise, at a packet sender device, adding a flow control identifier to a packet and transmitting a packet with the packet flow control identifier to a packet receiver device over a data path. Thereafter, the packet receiver device may receive, from the packet receiver device, flow control data that includes a received flow control identifier generated in response to the sent flow control identifier. The sent flow control identifier may then be compared with the received flow control identifier and a state of a receiver buffer at the receiver packet device may be estimated based on the comparison. In an example embodiment, at the packet sender device, a flow control instruction may be added to the packet to instruct the packet receiver device to enter a “no transmit” state.