Flow Processing Order Control for Virtual Router Memory Access
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Solution Overview
Problem
In virtual routers, the updating of flow table counter values is often slower than the registration of these values, leading to potential cache overflow and performance degradation due to the structural limitations of dynamic random-access memory (DRAM), where ROW address changes cause delays in memory access.
Innovation Solution
The implementation of a burst control circuit that manages flows with the same ROW address, allowing for consecutive processing and reducing ROW address switching, thereby minimizing memory access delays and improving performance by using a ROW address management table and update circuit to control the order of flow processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the flow table counter values are updated by sequentially processing each flow, then the counter values can be updated accurately, but the updating speed becomes slower than the registration speed, causing cache overflow
Solution Approach 1:
The patent pre-calculates and stores the next ROW address in a register before initiating memory access. This preliminary preparation allows the system to immediately continue accessing the same ROW address when the current access is complete, without waiting for address calculation and switching delays, thereby increasing update speed while maintaining accuracy
Solution Approach 2:
The patent implements continuous processing of flows that share the same ROW address by eliminating idle waiting time between accesses. The system maintains an uninterrupted access sequence to the same memory ROW, maximizing the utilization of memory bandwidth and preventing cache overflow through sustained high-speed updates
2Adaptability or versatility
If the ROW address is switched frequently to process different flows, then all flows can be processed, but memory access delays increase due to ROW address switching overhead
Solution Approach 1:
The patent groups and processes multiple flows that map to the same ROW address together in a single continuous memory access sequence. By merging these flows into one processing batch, the system eliminates repeated ROW address switching overhead while still handling diverse flow types, thus reducing time loss without sacrificing processing coverage
Solution Approach 2:
The system pre-identifies and groups flows with the same ROW address before processing, and pre-loads the next ROW address into the register in advance. This preliminary organization allows the memory controller to execute long sequential access patterns without interruption, minimizing address switching delays while maintaining comprehensive flow processing capability
Data Source
AI summary
An information processing apparatus includes a memory in which route information in flow control is stored, and in which flows that include a same ROW address as access destinations are grouped and stored when counter values managed in the route information are updated, and a processor coupled to the memory and configured to rearrange an order of a plurality of flows and access the memory consecutively for the plurality of flows that include the same ROW address as access destinations to update the counter values.