Flowlet Scheduler Queues for Ordered Multicore Packet Balancing

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Solution Overview

Problem

Existing packet scheduling mechanisms in communication networks face inefficiencies due to unpredictable packet reordering caused by processing concurrency, leading to reduced throughput and congestion, especially when flows are pinned to specific processing units and unbalanced workloads occur.

Innovation Solution

A packet order work scheduler (POWS) assigns packets to scheduler queues, ensuring each flow is dedicated to a specific processing unit until a queue-reallocation event, using age counters to dynamically rebalance workload across multiple processing paths without complex circuitry or software logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If each packet flow is fixed to a specific processing unit to avoid packet reordering, then packet order is preserved, but workload becomes unbalanced and processing parallelism is reduced

Engineering Contradiction:
Improvepacket orderVSAvoidprocessing parallelism
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic flow-to-processing-unit assignment where flows are not permanently pinned but can be reallocated based on current queue depths and age counters. This allows the system to adapt to changing workload conditions, maintaining packet order for active flows while enabling load balancing across processing units by migrating flows between units as needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses age counters as a parameter to track how long flows have been assigned to processing units. When age counters reach certain thresholds or when queue depths indicate imbalance, the system changes the assignment parameters by reallocating flows to different processing units, thus maintaining both packet order and processing parallelism.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple processing units are used to increase processing parallelism, then throughput is improved, but packet reordering occurs due to different processing paths

Engineering Contradiction:
Improveprocessing parallelismVSAvoidpacket order
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the packet processing system into multiple processing units, each handling specific flows at any given time. This segmentation allows parallel processing while maintaining packet order within each segment (processing unit), as each unit processes its assigned flows sequentially or in a controlled manner.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces scheduler queues as intermediary structures between the network interface and processing units. These queues act as buffers that decouple the parallel processing units from the packet arrival stream, allowing packets to be reordered into their original sequence before being delivered to the network, thus eliminating reordering issues while maintaining processing parallelism.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If software application programs are used to dictate packet ordering requirements, then packet order can be maintained for selected packets, but system complexity and cost increase

Engineering Contradiction:
Improvepacket orderVSAvoidsoftware logic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service packet scheduling mechanism where the system automatically tracks flow states, manages queue assignments, and performs load balancing without requiring external software application programs to dictate ordering requirements. The age counters and queue depth metrics enable the system to self-regulate packet ordering and processing distribution.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces complex software-based packet ordering mechanisms with a simpler hardware-oriented approach using dedicated processing units and scheduler queues. This substitution reduces the need for complex software logic by implementing ordering guarantees through the structural design of the processing architecture itself.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If flows are pinned to processing units permanently, then packet order is maintained, but the system cannot react to traffic spikes leading to link congestion

Engineering Contradiction:
Improvepacket orderVSAvoidresponse to traffic changes
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic flow assignment where flows are not permanently pinned to processing units but can be reallocated based on current system conditions. Age counters track the duration of assignments, and when traffic patterns change or congestion is detected, the system can migrate flows between processing units to balance load, thereby maintaining packet order while adapting to traffic spikes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250247166A1Flowlet scheduler for multicore network processors
Publication Date: 2025.07.31 MARVELL ASIA PTE LTD
  • US20250247166A1 patent drawing
  • US20250247166A1 patent drawing
  • US20250247166A1 patent drawing

AI summary

Systems and methods of using a packet order work scheduler (POWS) to assign packets to a set of scheduler queues for supplying packets to parallel processing units. A processing unit and the associated scheduler queue are dedicated to a specific flow until a queue-reallocation event, which may correspond to the associated scheduler queue being idle for at least a certain interval as indicated by its age counter, or the queue being the least recently used, when a new flow arrives. In this case, the scheduler queue and the associated processing unit may be reallocated to the new flow and disassociated with the previous flow. As a result, dynamic packet workload balancing can be advantageously achieved across the multiple processing paths.