Flowpro Machine Parallel Asynchronous Circuit Design
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Solution Overview
Problem
Current asynchronous chip design methodologies are complex and costly due to difficulties in design and debugging, leading to longer development times compared to synchronous designs, despite offering power and speed advantages, as they lack a master clock signal which complicates signal propagation and requires additional acknowledgment signals.
Innovation Solution
The introduction of the Flowpro Machine design model, which employs a parallel asynchronous stateless event model, simplifies design by eliminating the need for a master clock and request-acknowledge signals, allowing for easier debugging and reduced power consumption through asynchronous event modeling and parallel flowchart execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous design is used to reduce power consumption and increase processor speed, then energy efficiency and processing speed are improved, but device complexity and debugging difficulty increase significantly
Solution Approach 1:
The patent extracts and eliminates the master clock signal from the system, transitioning from synchronous to asynchronous design. This removes the need for clock distribution networks and timing synchronization, reducing power consumption while fundamentally changing the design approach to event-driven operation
Solution Approach 2:
The patent introduces Flowpro Machines as an intermediary computational model that bridges software algorithms and hardware implementation. This flowchart-based model serves as a mediator that simplifies the design process by providing a visual, executable specification that automatically translates to hardware, reducing design complexity despite the asynchronous architecture
2Use of energy by moving object
If asynchronous design eliminates the master clock signal to reduce power consumption, then energy efficiency is improved, but signal propagation control and debugging become more difficult
Solution Approach 1:
The patent implements self-service debugging capabilities where the Flowpro Machine simulation automatically generates execution traces and timing information. The system serves its own debugging needs by providing built-in visualization tools that show the sequence of operations and data flow, eliminating the need for external complex debugging equipment
Solution Approach 2:
The patent performs preliminary simulation and verification of the asynchronous design using Flowpro Machines before hardware implementation. By executing the flowchart model in software first, designers can detect and correct logic errors, timing issues, and design flaws before committing to hardware, significantly reducing debugging difficulty in the physical implementation
3Reliability
If traditional asynchronous design requires request-acknowledge signals for state validation, then reliability is improved, but device complexity and communication overhead increase
Solution Approach 1:
The patent extracts and removes the request-acknowledge signal handshake mechanism from the asynchronous design. By eliminating this formal verification protocol, the design achieves lower complexity and reduced communication overhead while maintaining reliability through the event-driven nature of Flowpro Machines that naturally ensure proper state transitions
Solution Approach 2:
The patent uses Flowpro Machine flowcharts as a copy or representation of the hardware behavior. The flowchart model mirrors the actual hardware operation, allowing verification and debugging in the software domain without requiring complex hardware verification protocols like request-acknowledge signals
4Adaptability or versatility
If multiple model translations are performed from software to hardware, then adaptability is improved, but loss of information and bug introduction increase
Solution Approach 1:
The patent makes the Flowpro Machine flowchart universal by enabling it to serve multiple functions: it is both the software specification and the hardware implementation model. The same flowchart can be simulated on a Turing machine for algorithm verification and downloaded to a Flowpro Machine chip for hardware execution, eliminating the need for separate software and hardware models and preventing information loss in translation
Data Source
AI summary
Devices, systems, and methods are disclosed that are configured to execute functions using synthesized parallel stateless asynchronous flowcharts. The flowcharts include one or more test objects, action objects, and/or task objects. Each of the objects in the flowcharts to be executed sets out an atomic path, which is a sequence of functions with one or more elements. The disclosed processing circuits are configured to execute the functions/instructions set forth in the flowcharts by following each atomic path. In some embodiments, the processing circuits execute the one or more flowcharts in an order determined during processing (i.e., “on the fly”). In these and other embodiments, the disclosed processing circuits transform or restore elements of the one or more flowcharts with or without human intervention.