Fluorine Dopant Distribution for Semiconductor Flicker Noise Reduction

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Solution Overview

Problem

Current semiconductor devices face increased flicker noise due to excessive oxide traps in dielectric layers, with existing solutions only mitigating high-frequency noise by filling traps at the interface, leaving low-frequency noise unaddressed.

Innovation Solution

A semiconductor structure with a polysilicon layer on a dielectric layer, where fluorine dopant concentrations follow a Gaussian distribution from top to bottom, with progressively decreasing peak concentrations, achieved through ion implantation and thermal processing, allowing fluorine dopant to fill oxide traps across the entire dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation processes with different implantation depths are performed, then comprehensive filling of oxide traps across the entire dielectric layer is achieved, but process complexity increases

Engineering Contradiction:
Improvecomprehensive oxide trap fillingVSAvoidion implantation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple ion implantation processes into a coordinated sequence that achieves comprehensive oxide trap filling. By combining processes with different implantation depths, concentrations, and energy levels, the method accomplishes what a single process cannot, while the thermal process subsequently integrates the dopant distribution

Inventive Principle:
Principle #5Merging (Combining)

2Object-affected harmful factors

If fluorine dopant concentration is increased to fill more oxide traps, then flicker noise mitigation improves, but dopant diffusion control becomes more difficult

Engineering Contradiction:
Improveflicker noise levelVSAvoiddopant concentration distribution control
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing ion implantation processes that strategically place fluorine dopant at specific depths and concentrations before final thermal processing. This preliminary positioning ensures that when thermal diffusion occurs, the dopant distributes optimally to fill oxide traps throughout the dielectric layer without excessive concentration in any single region, maintaining manufacturing precision while achieving effective noise mitigation

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates flicker noise across both high and low frequency ranges by ensuring comprehensive filling of oxide traps, enhancing semiconductor device performance.

Implementation Method 1

Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different.

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

After the ion implantation processes, a thermal process is performed to the polysilicon layer. the fluorine dopant in the polysilicon layer is diffused into the dielectric layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS10879361B2Method for manufacturing semiconductor structure
Publication Date: 2020.12.29 UNITED MICROELECTRONICS CORP
  • US10879361B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.