Fluorine Doped Polysilicon Gate for Threshold Voltage Control
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face challenges in controlling the threshold voltage of transistors as devices scale down, leading to variations and degrading performance, particularly due to short channel effects, with existing methods either raising threshold voltage or compromising device performance.
Innovation Solution
A method involving fluorine implantation into a polysilicon layer over a gate dielectric layer structure, followed by patterning and formation of source and drain regions, to create a fluorine dopant profile that reduces the dependency of threshold voltage on gate length, thereby stabilizing and flattening the voltage profile without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication techniques are used to scale down transistor devices, then device size is reduced, but threshold voltage control deteriorates due to short channel effects
Solution Approach 1:
The patent applies local quality by creating a non-uniform fluorine dopant concentration profile within the gate dielectric layer. The fluorine concentration varies through the thickness of the gate dielectric, with higher concentration near the semiconductor substrate interface and lower concentration toward the polysilicon gate electrode. This localized variation in dopant concentration allows precise control of threshold voltage in scaled-down devices without requiring changes to overall device geometry
Solution Approach 2:
The patent employs parameter changes by adjusting the fluorine implantation energy and dosage to control the depth and concentration of fluorine dopants in the gate dielectric layer. By varying these implantation parameters, the threshold voltage can be precisely tuned for different device applications while maintaining consistent device geometry. The fluorine implantation creates different dopant profiles (e.g., box profile, gradient profile) depending on implantation conditions
2Stability of the object's composition
If fluorine implantation is performed into the gate dielectric layer, then threshold voltage dependency on gate length is reduced, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing fluorine implantation into the gate dielectric layer before gate electrode formation. This allows the dopant profile to be established in advance, ensuring uniform threshold voltage characteristics across the entire gate structure before subsequent processing steps. The preliminary dopant implantation simplifies later process steps and reduces the need for additional threshold voltage adjustment operations
Solution Approach 2:
The fluorine dopant acts as an intermediary element that mediates between the gate dielectric layer and the threshold voltage characteristic. By introducing fluorine as a controllable dopant, the patent creates an intermediate layer of control that allows precise adjustment of threshold voltage without directly modifying the gate electrode or semiconductor substrate. This intermediary approach simplifies the overall fabrication process by decoupling threshold voltage control from device geometry definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces variations in threshold voltage across different gate lengths, maintaining high device performance and achieving a stable, flat threshold voltage dependency, even at advanced technology nodes with gate lengths less than 100 nm.
Implementation Method 1
performing a fluorine implantation process for implanting fluorine at least into the polysilicon layer
Data Source
AI summary
Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.