Fluorine-Doped Silicon Layer for 3D NAND Channel Holes
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Solution Overview
Problem
In three-dimensional NAND devices, the intrinsic channel effect increases threshold voltage distribution and reduces ON current due to increased channel resistance, limiting memory capacity and efficiency.
Innovation Solution
A fluorine-doped silicon layer is deposited within the stack trenches to enable fluorine diffusion and passivate the Si channel/tunnel SiO interface, improving ON current and reducing power requirements by narrowing the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If logical scaling is used to store more bits in a cell, then memory capacity increases, but threshold voltage distribution increases and ON current decreases
Solution Approach 1:
The patent applies local quality by introducing fluorine doping specifically at the channel/tunnel oxide interface region rather than uniformly throughout the structure. This localized modification targets the specific area where interface states cause threshold voltage spread, providing improved electrical characteristics where needed without affecting other regions of the memory cell.
Solution Approach 2:
The patent changes the chemical composition parameter by introducing fluorine atoms into the silicon layer at the channel/tunnel oxide interface. This parameter change modifies the electrical properties of the interface, reducing interface states and thereby narrowing threshold voltage distribution while maintaining the ability to store multiple bits.
2Quantity of substance
If logical scaling is used to store more bits in a cell, then memory capacity increases, but ON current decreases due to increased channel resistance
Solution Approach 1:
The fluorine doping is applied locally at the channel/tunnel oxide interface to reduce interface states that cause trapping and scattering of carriers. This local improvement in interface quality reduces effective channel resistance and enhances ON current without requiring changes to the overall channel dimensions or structure.
Solution Approach 2:
By changing the chemical composition at the interface through fluorine doping, the electrical parameters of the channel are improved. The fluorine atoms passivate interface states, reducing carrier trapping and scattering, which directly improves ON current and reduces the power needed to control multiple states.
3Reliability
If fluorine-doped silicon layer is deposited, then ON current increases and threshold voltage distribution narrows, but process complexity increases
Solution Approach 1:
The fluorine-doped silicon layer is deposited as a preliminary step before final channel formation. By preparing the doped layer in advance, the patent enables subsequent processing steps to utilize the pre-formed doping profile, reducing the need for additional complex doping steps later in the process.
Solution Approach 2:
The fluorine-doped silicon layer acts as an intermediary structure that facilitates the transfer of fluorine atoms to the channel/tunnel oxide interface during thermal processing. This intermediary layer simplifies the overall process by providing a controlled source of fluorine rather than requiring direct interface modification techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fluorine-doped silicon layer increases ON current, enhances subthreshold swing, and reduces the power needed to control multiple states, allowing for more efficient wordline stacking and improved memory performance.
Implementation Method 1
A fluorine-doped silicon layer is deposited within the stack trenches to enable fluorine diffusion and passivate the Si channel/tunnel SiO interface
Implementation Method 2
annealing the vertical stack
Data Source
AI summary
Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch step layer, and annealing the vertical stack.