Fluorine Gate Etch Passivation for High-k Metal Gate Reliability
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Solution Overview
Problem
The introduction of high-k and metal gate materials in scaled CMOS technologies faces challenges due to severe threshold voltage instability and performance degradation, particularly in short channel devices, attributed to bulk defects and interface states in the high-k/metal gate stack, where conventional Fluorine incorporation methods like implantation can lead to uncontrolled oxide re-growth.
Innovation Solution
A method involving the introduction of highly reactive F ions and radicals during the metal gate etch using a Fluorine comprising plasma, such as SF6/O2, followed by a thermal treatment above 700°C, to replace Si—H and Hf—H bonds with Si—F and Hf—F bonds in the high-k dielectric, thereby passivating the dielectric layer without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fluorine implantation is used to passivate the high-k dielectric, then interface and bulk defects are reduced, but uncontrolled oxide re-growth occurs and multiple implantation steps are required
Solution Approach 1:
The patent combines the Fluorine introduction step with the existing metal gate etch process by using SF6/O2 plasma chemistry. This merging eliminates the need for separate Fluorine implantation steps while achieving effective passivation of the high-k dielectric, thereby reducing processing complexity without sacrificing reliability
Solution Approach 2:
The SF6/O2 plasma etch chemistry serves multiple functions simultaneously: it performs the metal gate etching function while also introducing Fluorine for dielectric passivation. This multi-functionality resolves the contradiction by making a single process step accomplish what previously required multiple dedicated steps
2Ease of manufacture
If conventional H passivation is used for the high-k dielectric, then processing is simpler, but passivation is not robust enough for high temperature CMOS processing
Solution Approach 1:
The patent changes the chemical parameter of the passivation layer by introducing Fluorine instead of Hydrogen. This parameter change transforms the passivation chemistry from weak Si-H/Hf-H bonds to strong Si-F/Hf-F bonds, achieving robust passivation that withstands high temperature processing while maintaining ease of manufacture through the integrated plasma process
3Reliability
If multiple Fluorine implantations are performed during gate stack deposition, then complete dielectric passivation is achieved, but oxide re-growth becomes uncontrolled
Solution Approach 1:
The patent performs Fluorine introduction during the metal gate etch step, which occurs after the high-k dielectric is already formed and stabilized. This preliminary action of introducing Fluorine at the appropriate process stage achieves passivation without causing uncontrolled oxide re-growth that would occur with multiple implantations during deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the lifetime and performance of semiconductor devices by reducing Bias Temperature Instability (BTI) and maintaining robust passivation throughout standard CMOS processing, with improved threshold voltage control and drive current in multiple gate devices.
Implementation Method 1
exposing said gate stack layers to a fluorine comprising plasma
Implementation Method 2
The novel method relies on the introduction of highly reactive F ions and radicals during the metal gate etch
Implementation Method 3
submitting said exposed gate stack layers to a thermal treatment, wherein the temperature is higher than 700° C.
Implementation Method 4
incorporate or replace the Si—H and Hf—H bonds (especially at the interface of the silicon substrate and HfO2) by Si—F and Hf—F bonds
Data Source
AI summary
A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.