Fluorine-Tuned Gate Dielectrics for Multi-Gate Threshold Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling integrated circuits while maintaining effective current control and suppressing short channel effects, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
A semiconductor device design incorporating a substrate with N-type and P-type regions, featuring active patterns and gate structures with varying fluorine concentrations in gate dielectric films, allowing for transistors with different threshold voltages and improved performance through the use of high dielectric materials and work function control films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with three-dimensional channels are used to increase integration density, then scaling capability is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate structure and second gate structure) that can be independently formed with different fluorine concentrations. This segmentation allows each gate to be optimized separately for its specific function while maintaining overall integration density
Solution Approach 2:
Different regions of the gate structure are assigned different fluorine concentrations to achieve local optimization. The first gate structure has a higher fluorine concentration for strong current control, while the second gate structure has a lower fluorine concentration for reduced short channel effects, allowing each region to perform its specific function optimally
2Productivity
If gate length is kept small to maintain scaling, then integration density is improved, but current control capability deteriorates
Solution Approach 1:
The fluorine concentration parameter in the gate dielectric film is changed to achieve different threshold voltages and current control characteristics. By adjusting the fluorine concentration in different gate structures, the patent achieves effective current control without increasing gate length, thus maintaining high integration density
3Ease of manufacture
If uniform fluorine concentration is used in all gate structures, then manufacturing complexity is reduced, but transistor performance uniformity deteriorates
Solution Approach 1:
Different gate structures are assigned different fluorine concentrations based on their specific functional requirements. The first gate structure uses higher fluorine concentration for N-type region optimization, while the second gate structure uses lower fluorine concentration for P-type region optimization, achieving uniform transistor performance across different regions
4Reliability
If high fluorine concentration is used to improve current control, then threshold voltage control is improved, but short channel effects increase
Solution Approach 1:
The gate structure is divided into multiple segments with different fluorine concentrations. The first gate structure with higher fluorine concentration provides strong threshold voltage control, while the second gate structure with lower fluorine concentration mitigates short channel effects, achieving both objectives simultaneously through segmented design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the scalability and reliability of multi-gate transistors by improving current control and reducing short channel effects, while enabling transistors with tailored threshold voltages for optimized performance.
Implementation Method 1
a fluorine (F) concentration of the second gate dielectric film is smaller than a fluorine (F) concentration of the first gate dielectric film
Data Source
AI summary
A semiconductor device includes a substrate including an N-type region and a P-type region, a first active pattern on the N-type region, a first gate structure on the N-type region, the first gate structure crossing the first active pattern and including fluorine (F), a second active pattern on the P-type region, and a second gate structure on the P-type region, the second gate structure crossing the second active pattern and including fluorine (F), where the first gate structure includes a first gate dielectric film on the first active pattern, and a first gate electrode on the first gate dielectric film, the second gate structure includes a second gate dielectric film on the second active pattern and a second gate electrode on the second gate dielectric film, and a fluorine (F) concentration of the second gate dielectric film is smaller than a fluorine (F) concentration of the first gate dielectric film.