Fluorine and Nitrogen Doped Substrates for IC Power-Performance Balance

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Solution Overview

Problem

Integrated circuit devices face challenges in balancing power consumption and performance as they shrink in size, with conventional methods requiring substantial changes to manufacturing processes and struggling to control current leakage effectively.

Innovation Solution

The use of fluorine and nitrogen doping in substrates before gate insulator formation to modify dielectric characteristics, allowing for precise control of power consumption and performance without altering standard manufacturing steps, by implanting fluorine to reduce gate leakage and nitrogen to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional manufacturing methods are used to include more circuits on each chip, then device density increases, but power consumption and performance balancing becomes more difficult to achieve

Engineering Contradiction:
Improvedevice densityVSAvoidpower and performance balancing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies local quality by selectively doping different regions of the substrate with fluorine or nitrogen at the gate insulator interface. Specifically, first regions are doped with fluorine to reduce power leakage, while second regions are doped with nitrogen to enhance performance. This localized doping approach allows each region to be optimized for its specific function, enabling power-performance balancing across the chip without requiring substantial changes to the overall manufacturing process.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If fluorine doping is applied to reduce power leakage, then power consumption decreases, but manufacturing process complexity increases

Engineering Contradiction:
Improvepower leakageVSAvoidmanufacturing process complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by performing the dopant implantation into the substrate before the gate insulator formation step. This sequencing allows the dopants to be incorporated into the substrate in advance, and then the gate insulator is formed over the already-doped regions. This approach integrates the doping process into the existing manufacturing flow without requiring additional complex steps after gate insulator formation, thereby reducing power leakage while maintaining manufacturing simplicity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple-thickness gate dielectrics are used to balance power and performance, then power consumption and performance are balanced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvepower and performance balanceVSAvoidgate dielectric structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the electrical properties of the substrate at the gate insulator interface through dopant concentration control rather than changing the physical thickness of the gate dielectric. By adjusting the concentration and type of dopants (fluorine or nitrogen) in the substrate, the patent achieves the desired power and performance balance without requiring multiple gate dielectric thicknesses. This maintains a uniform gate dielectric structure while achieving the functional differentiation needed for power-performance optimization.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces gate leakage by up to five times and allows for fine-tuning of power and performance characteristics across the chip, achieving balanced power consumption and performance without the need for multiple-thickness gate dielectrics, thus optimizing integrated circuit design efficiently.

Implementation Method 1

A predetermined concentration of fluorine is within the substrate at a position where the gate insulator contacts the substrate

Methodology Applied
Scientific EffectFluorine doping: Dopants

Implementation Method 2

Second sets of the integrated circuit transistor structures within the integrated circuit device have a second dopant in the substrate at a position where a corresponding gate insulator of the second sets of the integrated circuit transistor structures contacts the substrate

Methodology Applied
Scientific EffectNitrogen doping: Dopants

Data Source

PatentUS8431955B2Method and structure for balancing power and performance using fluorine and nitrogen doped substrates
Publication Date: 2013.04.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8431955B2 patent drawing
  • US8431955B2 patent drawing
  • US8431955B2 patent drawing

AI summary

Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design.