Fluorocarbon Etch Selectivity for Nanosheet FET Channel Release
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Solution Overview
Problem
The challenge in semiconductor fabrication lies in achieving sufficient etch selectivity between un-doped and doped semiconductors, particularly in processes like channel release for nanosheet/nanowire FETs, where conventional methods cause damage to source/drain regions due to etch gas penetration through thin, porous inner spacers.
Innovation Solution
A plasma-less etch process enhanced with fluorocarbon pretreatment is used to selectively etch un-doped silicon germanium relative to boron-doped silicon germanium, employing gases like C2F6, C4F8, HF, and F2 without plasma, which passivates the doped semiconductor and ensures selective etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional plasma etching is used to remove sacrificial layer, then etching speed is improved, but source/drain regions are damaged due to etch gas penetration through thin porous inner spacers
Solution Approach 1:
A fluorocarbon-based pretreatment step is performed before the main etching process to deposit a protective layer on the inner spacer surface. This preliminary action creates a barrier that prevents etch gas penetration during subsequent etching, protecting source/drain regions while maintaining etching efficiency
Solution Approach 2:
The fluorocarbon-based inner spacer hard mask acts as an intermediary protective layer between the etch gas and the inner spacer. This intermediate layer blocks the harmful interaction between etch gas and the porous inner spacer, preventing source/drain damage while allowing the etching process to proceed
2Length of moving object
If inner spacer thickness is reduced to improve device scaling, then device density is improved, but etch gas penetration increases causing source/drain damage
Solution Approach 1:
The fluorocarbon-based pretreatment is applied beforehand to deposit a protective hard mask layer on the inner spacer surface. This preliminary protective layer compensates for the reduced thickness of the inner spacer, preventing etch gas penetration even when the inner spacer is scaled down to enable device scaling
Solution Approach 2:
A thin fluorocarbon-based hard mask film is deposited on the inner spacer to provide protective functionality. This thin film acts as a flexible barrier that prevents etch gas penetration while allowing the inner spacer itself to be made thinner for device scaling
3Object-affected harmful factors
If fluorocarbon pretreatment is applied to protect doped semiconductor, then source/drain damage is prevented, but process complexity increases
Solution Approach 1:
The fluorocarbon-based pretreatment and inner spacer hard mask formation steps are merged into a single process step. This combination reduces process complexity by eliminating the need for separate pretreatment and hard mask deposition steps, while still providing the necessary protection against source/drain damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method mitigates source/drain damage, improving device yield by enabling precise etch selectivity in complex semiconductor structures like GAAFETs and stacked FETs, particularly in channel release processes.
Implementation Method 1
exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma
Implementation Method 2
exposing the substrate to an etch gas including fluorine in the absence of plasma to etch the sacrificial layer selectively
Data Source
AI summary
A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.