Fly-By Topology Signal Reflection Mitigation

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Solution Overview

Problem

In electronic devices, the fly-by topology for mounting semiconductor components leads to signal waveform disturbances due to long branch wirings, causing undesired signal reflection and deteriorating waveform quality, especially when high-speed memory devices and control devices are directly mounted on a common substrate.

Innovation Solution

The implementation of chip resistors in series within the branch wirings of the fly-by topology helps alleviate signal reflection issues, even with long branch paths, by optimizing the wiring configuration and reducing signal distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices are directly mounted on a mother board to increase storage capacity, then the storage capacity increases, but the mother board size increases

Engineering Contradiction:
Improvestorage capacityVSAvoidmother board size
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent applies nesting by mounting multiple memory devices on an interposer substrate first, then mounting the entire interposer substrate onto the mother board. This nested structure allows high-density memory integration while keeping the mother board footprint small, as the interposer acts as a compact intermediate platform that consolidates multiple memory devices in a reduced space.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of energy

If a fly-by topology is used to reduce wiring load, then the wiring load is reduced, but signal waveform quality deteriorates due to long branch wirings causing signal reflection

Engineering Contradiction:
Improvewiring loadVSAvoidsignal waveform quality
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The interposer substrate serves as an intermediary between the mother board and memory devices, providing a optimized wiring structure. The interposer includes through-hole wirings that create shorter signal paths and better impedance control compared to long branch wirings on the mother board, thus reducing signal reflection while maintaining the fly-by topology's wiring load advantages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes three-dimensional wiring structures including through-hole wirings that extend vertically through the interposer substrate. This dimensional transition from planar surface mounting to vertical through-hole connections reduces the effective signal path length and improves signal integrity by moving critical connections to different spatial dimensions, thereby reducing the harmful effects of long branch wirings.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses waveform quality deterioration, enabling high-speed access and reliable interface signal performance between memory devices and control devices, while also considering the increased storage capacity and reduced size requirements of modern electronic devices.

Implementation Method 1

signal waveform disturbances due to long branch wirings, causing undesired signal reflection

Methodology Applied
Scientific EffectSignal reflection: Reflection

Implementation Method 2

The implementation of chip resistors in series within the branch wirings of the fly-by topology helps alleviate signal reflection issues

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS9997231B2Electronic device
Publication Date: 2018.06.12 RENESAS ELECTRONICS CORP
  • US9997231B2 patent drawing
  • US9997231B2 patent drawing
  • US9997231B2 patent drawing

AI summary

An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.